AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 450

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 34-5. Elementary Time Unit (ETU)
34.6.2
34.6.3
34.6.3.1
6289C–ATARM–28-May-09
Receiver and Transmitter Control
Synchronous and Asynchronous Modes
Transmitter Operations
ISO7816 I/O Line
ISO7816 Clock
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit
in the Control Register (US_CR). However, the receiver registers can be programmed before the
receiver clock is enabled.
After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the
Control Register (US_CR). However, the transmitter registers can be programmed before being
enabled.
The Receiver and the Transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by
setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register
(US_CR). The software resets clear the status flag and reset internal state machines but the
user interface configuration registers hold the value configured prior to software reset. Regard-
less of what the receiver or the transmitter is performing, the communication is immediately
stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and
TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the
USART waits until the end of reception of the current character, then the reception is stopped. If
the transmitter is disabled while it is operating, the USART waits the end of transmission of both
the current character and character being stored in the Transmit Holding Register (US_THR). If
a timeguard is programmed, it is handled normally.
The transmitter performs the same in both synchronous and asynchronous operating modes
(SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two
stop bits are successively shifted out on the TXD pin at each falling edge of the programmed
serial clock.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register
(US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The
parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none
parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If
written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The num-
ber of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in
asynchronous mode only.
on SCK
on TXD
AT91SAM9R64/RL64 Preliminary
ISO7816 Clock Cycles
FI_DI_RATIO
1 ETU
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