AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 843
AT91SAM9R64-CU
Manufacturer Part Number
AT91SAM9R64-CU
Description
MCU ARM9 64K SRAM 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9R64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 3 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
49
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
144LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9R64-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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43.10.4
Register Name:
Access Type:
• TSSHTIM: Sample & Hold Time for Touch Screen Channels
Programming 0 for TSSHTIM gives a Touch Screen Sample & Hold Time equal to (2/ADCCLK).
43.10.5
Register Name:
Access Type:
• CHx: Channel x Enable
0 = No effect.
1 = Enables the corresponding channel.
6289C–ATARM–28-May-09
Touch Screen Sample & Hold Time = (TSSHTIM+1) / ADCCLK
31
23
15
31
23
15
–
–
–
7
–
–
–
–
7
–
TSADCC Touch Screen Register
TSADCC Channel Enable Register
30
22
14
30
22
14
TSADCC_TSR
Read/Write
–
–
–
6
–
TSADCC_CHER
Write-only
–
–
–
6
–
CH5
29
21
13
29
21
13
–
–
–
5
–
–
–
–
5
CH4
28
20
12
28
20
12
–
–
–
4
–
–
–
–
4
AT91SAM9R64/RL64 Preliminary
CH3
27
19
11
27
19
11
–
–
3
–
–
–
–
3
CH2
26
18
10
26
18
10
–
–
–
–
–
–
2
2
TSSHTIM
CH1
25
17
25
17
–
–
–
–
–
–
9
1
9
1
CH0
24
16
24
16
–
–
–
–
–
–
8
0
8
0
843
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