AT91SAM9261B-CU Atmel, AT91SAM9261B-CU Datasheet - Page 41

• Manufacturer Part Number: AT91SAM9261B-CU
• Description: MCU ARM9 ULTRA LOW PWR 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 240MHz
• Total Internal Ram Size: 160KB
• # I/os (max): 96
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.2/1.8/3.3V
• Operating Supply Voltage (max): 1.32/1.95/3.6V
• Operating Supply Voltage (min): 1.08/1.65/2.7/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 217
• Package Type: LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 160 KB
• Interface Type: JTAG,SPI, SSC, TWI, UART
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 96
• Ram Memory Size: 160KB
• Cpu Speed: 190MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

13. Revision History
Table 13-1.
6062LS–ATARM–23-Mar-09
Doc.
Rev.
6062AS
6062BS
6062CS
Source
CSR 04-370
CSR 04-371
CSR 04-376
CSR 04-446
CSR 04-447
CSR 04-461
CSR 04-475
CSR 05-023
CSR 05-024
CSR 05-398
CSR 05-481
CSR 05-496
CSR 05-487
Revision History
Comments
Date: 02-Jun-05
Change to Additional Embedded Memories in
Consumption” on page
Change to AIC,
Peripheral,” on page
modified in
Changed ROM access to single cycle in
on page
Replaced “PDMA” with “PDC” throughout. Replaced “Peripheral DMA” with “Peripheral DMA Controller”
throughout.
New pinout for 217-ball LFBGA package, Table 2 updated.
Updated
Removed “Embedded Software Services” on page 18.
Changed min voltage level for VDDIOM and VDDIOP to 2.7V throughout. Corrected nominal voltage
level for VDDIOP and VDDIOP in
Added information on chip select assignment management in
page
Added information on configuration management of embedded pad pull-up in
page
Throughout document: All references to SmartMedia removed and replaced by NAND Flash. All signals
SMxx changed to NANDxx.
Throughout document: Package now qualified as RoHS-compliant
Changed pull-up resistor level to 10 kOhm in
Changed typical conditions for VDDCORE to 1.2V in
Corrected BMS state in
Date: 15-Nov-05
Changed SPI pin names in
Description by Peripheral,” on page
Table 10-3, “Multiplexing on PIO Controller B,” on page 32
Controller C,” on page
Updated A22 pin in
Changed value of programmable pull-up resistor in
page
Updated
Qualified/Internal: 23-Aug-04
Corrected BMS reset condition for ROM access in
Added NTRST signal
34.
38.
12.
17.
Section 8.1.2 ”Boot Program” on page
Table 12-1, “AT91SAM9261 Ordering Information,” on page
Table 4-1 on page
“Features” on page
Figure 2-1, “AT91SAM9261 Block Diagram,” on page
5, Change to
to“Block Diagram” on page
33.
11. Change to
Table 8-3, “Internal Memory Mapping,” on page
Figure 2-1, “AT91SAM9261 Block Diagram,” on page
10. Change to
Section 5.1 “Power Supplies” on page
Section 10.3.1.5 “NAND Flash Interface” on page
1, SMCS signal added to
5,
Table 8-3 on page
Table 10-2, “Multiplexing on PIO Controller A,” on page
“Features” on page 1
Section 6.4 “PIO Controller A, B and C Lines” on page
“JTAG Port Pins” on page
“Features” on page
AT91SAM9261 Preliminary
20.
4. NTRST signal added to
Section 8.1.1.2 “Internal ROM” on page
Section 6.4 “PIO Controller A, B and C Lines” on
Section 5.2 “Power Consumption” on page
18.
and
Table 3-1, “Signal Description by
Section 10.4 “External Bus Interface” on
and
Table 10-4, “Multiplexing on PIO
1. Change to
Section 8.1 “Embedded Memories”
40.
11.
18.
11.
4.
Table 3-1 on page
Section 10.13 “USB” on
Section 5.2 “Power
4,
Table 3-1, “Signal
30.
19.
31,
5. F1
11.
12.
41