LPC1343FBD48,151 NXP Semiconductors, LPC1343FBD48,151 Datasheet - Page 216

• Manufacturer Part Number: LPC1343FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 40
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4945; 935289652151

NXP Semiconductors
Table 230. Slave Receiver mode
UM10375
User manual
Status
Code
(I2CSTAT)
0x60
0x68
0x70
0x78
0x80
0x88
0x90
Status of the I
and hardware
Own SLA+W has
been received; ACK
has been returned.
Arbitration lost in
SLA+R/W as master;
Own SLA+W has
been received, ACK
returned.
General call address
(0x00) has been
received; ACK has
been returned.
Arbitration lost in
SLA+R/W as master;
General call address
has been received,
ACK has been
returned.
Previously addressed
with own SLV
address; DATA has
been received; ACK
has been returned.
Previously addressed
with own SLA; DATA
byte has been
received; NOT ACK
has been returned.
Previously addressed
with General Call;
DATA byte has been
received; ACK has
been returned.
2
C-bus
Application software response
To/From I2DAT
No I2DAT action
or
No I2DAT action
No I2DAT action
or
No I2DAT action
No I2DAT action
or
No I2DAT action
No I2DAT action
or
No I2DAT action
Read data byte or X
Read data byte
Read data byte or 0
Read data byte or 0
Read data byte or 1
Read data byte
Read data byte or X
Read data byte
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
To I2CON
STA STO SI
X
X
X
X
X
X
X
X
X
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Chapter 12: LPC13xx I2C-bus controller
Next action taken by I
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
Switched to not addressed SLV mode; no
recognition of own SLA or General call
address.
Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
I2ADR[0] = logic 1.
Switched to not addressed SLV mode; no
recognition of own SLA or General call
address. A START condition will be
transmitted when the bus becomes free.
Switched to not addressed SLV mode;
Own SLA will be recognized; General call
address will be recognized if
I2ADR[0] = logic 1. A START condition
will be transmitted when the bus becomes
free.
Data byte will be received and NOT ACK
will be returned.
Data byte will be received and ACK will
be returned.
UM10375
© NXP B.V. 2010. All rights reserved.
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C hardware
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