LPC3131FET180,551 NXP Semiconductors, LPC3131FET180,551 Datasheet - Page 12

• Manufacturer Part Number: LPC3131FET180,551
• Description: IC ARM9 MCU 180MHZ 180-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3131FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C/I2S/UART/USB
• Maximum Clock Frequency: 180 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC3131-PL
• Development Tools By Supplier: OM11028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4850 - KIT EVAL FOR LPC313X568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4697; 935288014551; LPC3131FET180-S

NXP Semiconductors
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[6]
Table 5.
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Table 6:
LPC3130_3131
Preliminary data sheet
Supply
domain
SUP1
SUP3
SUP4
SUP5
SUP8
Cell type
DIO1
DIO2
DIO4
IICC
IICD
AIO1
AIO2
AIO3
CS1
CS2
PS1
PS2
CG1
CG2
PG1
The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for
UART flow control, they can also be selected to be used for an alternative function: SPI chip select signals (SPI_CS_OUT1 and
SPI_CS_OUT2).
To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins TRST_N and JTAGSEL must be LOW at power-on reset, see
UM10314 JTAG chapter for details.
When the SDRAM is used, the supply voltage of the NAND flash, SDRAM, and the LCD Interface must be the same, i.e. SUP4 and
SUP8 should be connected to the same rail. (See also
Supply domains
I/O pads
Voltage range
1.0 V to 1.3 V
2.7 V to 3.6 V
1.65 V to 1.95 V (in 1.8 V mode)
2.5 V to 3.6 V (in 3.3 V mode)
4.5 V to 5.5 V
1.65 V to 1.95 V (in 1.8 V mode)
2.5 V to 3.6 V (in 3.3 V mode)
Pad type
bspts3chp
bpts5pcph
mem1
bsptz40pchp
iic3m4scl
iic3mvsda
apio3v3
apio
apiot5v
vddco
vddi
vdde3v3
vdde
vssco
vssis
vsse
Function
Digital Input/Output Bidirectional 3.3 V; 3-state output; 3 ns slew rate control; plain
Digital Input/Output Bidirectional 5 V; plain input; 3-state output; CMOS with
Digital Input/Output Bidirectional 1.8 V or 3.3 V; plain input; 3-state output;
Digital Input/Output I
Digital Input/Output I
Analog Input/Output Analog input/output; protection to external 3.3 V supply rail
Analog Input/Output Analog input/output
Analog Input/Output Analog input/output; 5 V tolerant pad-based ESD protection
Core Supply
Core Supply
Peripheral Supply
Peripheral Supply
Core Ground
Core Ground
Peripheral Ground
All information provided in this document is subject to legal disclaimers.
Related supply pins
VDDI, VDDA12, USB_VDDA12_PLL Digital core supply
VDDE_IOC, ADC10B_VDDA33,
USB_VDDA33_DRV, USB_VDDA33
VDDE_IOA
USB_VBUS
VDDE_IOB
Rev. 1.04 — 27 May 2010
Section
Description
input; CMOS with hysteresis; programmable pull-up, pull-down,
repeater
programmable hysteresis; programmable pull-up, pull-down,
repeater
programmable hysteresis; programmable pull-up, pull-down,
repeater
-
-
-
-
-
-
-
2
2
C-bus; clock signal
C-bus; data signal
6.26.3.)
Low-cost, low-power ARM926EJ-S microcontrollers
Description
Peripheral supply
Peripheral supply for NAND flash
interface
Peripheral supply for
SDRAM/SRAM/bus-based LCD
USB VBUS voltage
LPC3130/3131
© NXP B.V. 2010. All rights reserved.
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