PXAG30KBA,512 NXP Semiconductors, PXAG30KBA,512 Datasheet - Page 9

• Manufacturer Part Number: PXAG30KBA,512
• Description: IC XA MCU 16BIT ROMLESS 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: XAr

Specifications of PXAG30KBA,512

• Core Processor: XA
• Core Size: 16-Bit
• Speed: 30MHz
• Connectivity: UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Processor Series: PXAG3x
• Core: 80C51
• Data Bus Width: 16 bit
• Data Ram Size: 512 B
• Interface Type: UART
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4340-5; 935270580512; PXAG30KBA; PXAG30KBA

*
1. At reset, the BCR register is loaded with the binary value 0000 0a11, where “a” is the value on the BUSW pin. This defaults the address bus
2. SFR is loaded from the reset vector.
3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0.
4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on the
6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.
7. The XA-G30 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide . All SFR accesses must be 8-bit operations. Attempts
Philips Semiconductors
NOTES:
2002 Mar 25
SWR*
T2CON*
T2MOD*
TH2
TL2
T2CAPH
T2CAPL
TCON*
TH0
TH1
TL0
TL1
TMOD
TSTAT*
WDCON*
WDL
WFEED1
WFEED2
NAME
NAME
XA 16-bit microcontroller family
512 B RAM, watchdog, 2 UARTs
SFRs are bit addressable.
size to 20 bits since the XA-G30 has only 20 address lines.
purposes in future XA derivatives. The reset value shown for these bits is 0.
condition found on the EA pin. Thus all PnCFGA registers will contain FF and PnCFGB registers will contain 00. When the XA begins
execution using external code memory, the default configuration for pins that are associated with the external bus will be push-pull. The
PnCFGA and PnCFGB register contents will reflect this difference.
to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte.
Software Interrupt Request
Timer 2 control register
Timer 2 mode control
Timer 2 high byte
Timer 2 low byte
Timer 2 capture register,
high byte
Timer 2 capture register,
low byte
Timer 0 and 1 control register
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
Timer 1 low byte
Timer 0 and 1 mode control
Timer 0 and 1 extended status
Watchdog control register
Watchdog timer reload
Watchdog feed 1
Watchdog feed 2
DESCRIPTION
DESCRIPTION
ADDRESS
ADDRESS
45C
45D
SFR
SFR
42A
418
419
459
458
45B
45A
410
451
453
450
452
41F
45F
45E
411
GATE
PRE2
MSB
2C7
TF2
2CF
TF1
2FF
357
287
28F
—
—
—
SWR7
PRE1
EXF2
2CE
2C6
TR1
28E
2FE
356
286
C/T
—
—
7
BIT FUNCTIONS AND ADDRESSES
RCLK0 TCLK0 EXEN2
RCLK1 TCLK1
SWR6
PRE0
2CD
2C5
28D
2FD
355
285
TF0
M1
—
SWR5
2CC
TR0
2FC
2C4
28C
354
284
M0
—
—
SWR4
GATE
2CB
2C3
28B
2FB
353
283
IE1
—
—
—
WDRUN
SWR3
T1OE
2CA
2C2
TR2
28A
2FA
352
282
C/T
IT1
—
WDTOF
SWR2
T2OE
C/T2
2C1
2C9
351
281
289
2F9
IE0
M1
—
CP/RL2
SWR1
DCEN
T0OE
XA-G30
LSB
2C0
2C8
280
2F8
350
288
IT0
M0
—
Product data
RESET
RESET
VALUE
VALUE
Note 6
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
x
x