Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 103

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

Table 45. Interrupt Request1 Register (IRQ1) and Interrupt Request1 Set register (IRQ1SET)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
FIELD
RESET
R/W
ADDR
Note: IRQ1SET at address FF_E035H is write only and used to set the interrupts identified.
Interrupt Request 1 Register
R/W1C
PAD7I
PAD7I
W
7
0
0
I2CI—I2C Interrupt Request
0 = No interrupt request is pending for the I2C.
1 = An interrupt request from the I2C is awaiting service. Writing 1 to this bit Resets it to 0.
SPII—SPI Interrupt Request
0 = No interrupt request is pending for the SPI.
1 = An interrupt request from the SPI is awaiting service. Writing 1 to this bit Resets it to 0.
ADCI—ADC Interrupt Request
0 = No interrupt request is pending for ADC.
1 = An interrupt request from ADC is awaiting service. Writing 1 to this bit Resets it to 0.
The interrupt request 1 (IRQ1) register (see
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the ZNEO
CPU. If interrupts are globally disabled (polled interrupts), the ZNEO CPU reads the
interrupt request 1 register to determine, if any interrupt requests are pending. Writing 1 to
the bits in this register clears the interrupt. The bits of this register are set by writing 1 to
the interrupt request 1 set regsiter (IRQ1SET) at address FF_E035H.
PADxI—Port A/D Pin x Interrupt Request
0 = No interrupt request is pending for GPIO port A/D pin x.
1 = An interrupt request from GPIO port A/D pin x is awaiting service. Writing 1 to these
bits Resets it to 0.
R/W1C
PAD6I
PAD6I
W
6
0
0
R/W1C
PAD5I
PAD5I
W
5
0
0
P R E L I M I N A R Y
R/W1C
PAD4I
PAD4I
W
4
0
0
FF_E034H
FF_E035H
Table
R/W1C
PAD3I
PAD3I
W
3
0
0
45) stores interrupt requests for both
R/W1C
PAD2I
PAD2I
W
2
0
0
Product Specification
ZNEO
R/W1C
PAD1I
PAD1I
Interrupt Controller
W
1
0
0
Z16F Series
R/W1C
PAD0I
PAD0I
W
0
0
0
88