Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 200

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
SCK (SSMD = 00,
Rx Data Register
Tx Data Register
Shift Register
MOSI, MISO
ESPI Interrupt
CLKPOL = 0,
PHASE = 0,
SSPO = 0)
RDRF
TDRE
I2S (Inter-IC Sound) Mode
This mode is selected by setting the SSMD field of the mode register to 010. The
and
Figure 38
of a fixed number of data bytes as defined in the DMA buffer descriptor or by software.
I
The SSV indicates whether the corresponding bytes are left or right channel data. The
SSV value must be updated when servicing the TDRE interrupt/request for the first byte in
a left or write channel frame. This is accomplished by performing a word write when
writing the first byte of the audio word, which updates both the ESPI data and transmit
data command words or by doing a byte write to update SSV followed by a byte write to
the data register. The SS signal leads the data by one SCK period.
If a DMA channel is controlling data transfer, each sequence of left (or right) channel byte
is considered a frame with a buffer descriptor. The SSV bit is defined in the buffer
descriptor command field and is automatically written to the transmit data command
2
S (Inter-IC Sound) mode is typically used to transfer left or right channel audio data.
Clkpol
Tx/Rx n-1
Tx n
Bit0
on page 185 with SS alternating between consecutive frames. A frame consists
bits of the control register must be set to 0. This mode is illustrated in
Rx n-1
Bit7
Figure 37. SPI mode (SSMD = 000)
Bit6
P R E L I M I N A R Y
Tx/Rx n
Tx n+1
Empty
Bit1
Enhanced Serial Peripheral Interface
Bit0
Product Specification
ZNEO
Bit7
Rx n
Tx/Rx n+1
Bit 6
empty
Z16F Series
Tx n+2
Phase
184