Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 339

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

®
ZNEO
Z16F Series
Product Specification
323
DBGHALT—Debug Halt mode
This status bit indicates if the CPU is stopped and in debug halt mode.
0 = Device is running
1 = CPU is in Debug Halt mode
DBGBRK—Debug break
This bit indicates if the CPU has reached a
instruction. This bit is set when a
BRK
BRK
instruction is executed. It is cleared when the DBGHALT control bit is written to zero.
HALT—HALT mode
0 = The device is not in HALT mode.
1 = The device is in HALT mode.
STOP—STOP mode
0 = The device is not in Stop mode.
1 = The device is in Stop mode.
RPEN—Read protect enabled
0 = Memory Read Protect is disabled.
1 = Memory Read Protect is enabled.
TDRF—Transmit Data register full
This bit is set when the transmit data register is full.
0 = Transmit Data register is empty
1 = Transmit Data register is full
RDRE—Receive Data register empty
This bit indicates when the receive data register is empty.
0 = Receive Data register is full.
1 = Receive Data register is empty.
Reserved
These bits are reserved and always read back zero.
PS022008-0810
P R E L I M I N A R Y
On-Chip Debugger