Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 242

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
Note:
•
•
Slave Read Transaction with Data DMA
In this transaction the I
•
•
•
•
•
•
•
If the master sends a Not Acknowledge prior to the last byte, software responds to the Not
Acknowledge interrupt by clearing the
The I
When the second DMA interrupt occurs, it indicates that the Nth byte is received. A
Clear the
The I
When the SAM interrupt occurs, set the
The DMA transfers the data to be transmitted to the master.
When the DMA interrupt occurs, the last byte is being transferred to the master. The
Clear the
Configure the selected DMA channel for I
Stop I
issues the STOP (or RESTART) condition.
DMACTL register for the last buffer to be transferred. Typically a single buffer with a
transfer length of N is defined.
error conditions. A Not Acknowledge interrupt occurs on the last byte transferred.
Slave mode transactions. The
master must send a Not Acknowledge for this last byte, setting the
I2CSTAT register and generating the I
bit set in I2CSTAT register) follows.
2
2
C interrupt must be enabled in the interrupt controller to alert software of any I
2
C Master/Slave must be configured as defined in the sections above describing
C interrupt occurs (
DMAIF
DMAIF
bit in the I2CMODE register.
bit in the I2CMODE register.
2
C Master/Slave operates as a slave, sending data to the master.
P R E L I M I N A R Y
SPRS
TXI
bit set in the I2CSTAT register) when the master
bit in the I2CCTL register must be cleared.
DMAIF
2
C interrupt. A Stop or Restart interrupt (
DMAIF
2
bit.
C transmit. The
bit in the I2CMODE register.
I
IEOB
2
C Master/Slave Controller
Product Specification
ZNEO
bit must be set in the
NCKI
Z16F Series
bit in the
SPRS
2
C
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