Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 325

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

®
ZNEO
Z16F Series
Product Specification
309
Trace Events
A trace event occurs anytime a CALL, RET, Interrupt, IRET, TRAP, JP, DJNZ, or Excep-
tion occurs. Trace takes four cycles each time a trace event occurs (five cycles for IRQ,
TRAP, and Exceptions).
Trace Buffer
The Trace Buffer is controlled by two registers: Trace Control (TRACECTL) and Trace
Address (TRACEADDR) register. The TRACECTL register is used to enable the trace
and select the size of the Trace Buffer. TRACEADDR selects the starting address for the
trace. The trace address is modulo-n based upon the size of the TRACESEL field in the
TRACECTL register. The modulo-n is zero aligned, which means that the trace buffer
always wraps to zero for the selected size. For example, if the TRACEADDR is set to
FFFFB050H and the TRACECTL is set to 81H, the Buffer is located from FFFFB000H to
FFFFB0FFH with the first trace event to be written to FFFFB050H. When the address
reaches FFFFB0FFH it will roll over to FFFFB000H.
Trace buffer sizes are 128, 256, 512, 1024, 2048, 4096, 8192, and 16384 bytes. Each trace
event requires eight bytes giving a minimum of 16 events to a maximum of 2048 events.
Only the Program Counter values are stored. Other information has to be inferred from the
source code by the trace debugger.
Trace Operation
On each trace event the current program counter is placed in memory pointed to by the
TRACEADDR. TRACEADDR increments by 4 and the next state of the program counter
is written to the TRACEADDR. TRACEADDR increments by 4 again. TRACEADDR
always points to the next data to be written. The lower two bits of the TRACEADDR are
always zero.
Extracting Trace Information
The trace information is extracted by reading the data from the selected trace memory
area. The data is then interpreted by the Trace Debugger software.
PS022008-0810
P R E L I M I N A R Y
On-Chip Debugger