EZ80F91NA050SG Zilog, EZ80F91NA050SG Datasheet - Page 193
EZ80F91NA050SG
Manufacturer Part Number
EZ80F91NA050SG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3870
EZ80F91NA050SG
EZ80F91NA050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050SG
Manufacturer:
ZILOG
Quantity:
20 000
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Table 96. UART Transmit Holding Registers
Table 97. UART Receive Buffer Registers
PS019215-0910
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
T
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
R
x
x
D
D
UART Receive Buffer Register
The bits in this register reflect the data received. If less than eight bits are programmed
for reception, the lower bits of the byte reflect the bits received, whereas upper unused
bits are 0. The Receive FIFO is mapped at this address. If the FIFO is disabled, this
buffer is only one byte deep.
These registers share the same address space as the UARTx_THR and UARTx_BRG_L
registers. See
UART Interrupt Enable Register
The UARTx_IER register is used to enable and disable the UART interrupts. The
UARTx_IER registers share the same I/O addresses as the UARTx_BRG_H registers. See
Table 98
Value
00h–FFh Transmit data byte.
Value
00h–FFh Receive data byte.
on page 185.
W
Description
X
X
R
7
7
Description
Table
W
X
X
R
6
6
97.
W
X
X
R
5
5
(UART0_RBR = 00C0h, UART1_RBR = 00 D0h)
W
X
X
R
(UART0_THR = 00C0h, UART1_THR = 00D0h)
4
4
W
R
X
X
3
3
Universal Asynchronous Receiver/Transmitter
W
R
X
X
2
2
W
R
X
X
1
1
Product Specification
W
R
X
X
0
0
eZ80F91 MCU
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