EZ80F91NA050SG Zilog, EZ80F91NA050SG Datasheet - Page 303
![IC ACCLAIM MCU 256KB 144-BGA](/photos/12/15/121558/269-144-bga_sml.jpg)
EZ80F91NA050SG
Manufacturer Part Number
EZ80F91NA050SG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3870
EZ80F91NA050SG
EZ80F91NA050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050SG
Manufacturer:
ZILOG
Quantity:
20 000
- Current page: 303 of 384
- Download datasheet (3Mb)
PS019215-0910
Note:
For an official description of an Ethernet packet, refer to IEEE 802.3 specification, Figure
3-1.
The descriptor table contains three entries: the next pointer (NP), the packet size
(Pkt_Size), and the packet status (Stat), as displayed in
NP is a 24-bit pointer to the start of the next packet. Pkt_Size contains the number of bytes
of data in the Ethernet packet, including the four CRC bytes, but does not contain the
seven descriptor table bytes. Stat contains the status of the packet. Stat differs for Transmit
and Receive packets. See
TWP
TWP
Descriptor
Ethernet
Pkt_Size
Packet
Table
Stat
NP
Figure 62. Descriptor Table Entries
Table 178
Figure 61. Descriptor Table
Offset
0007h
0000h
Offset
0005h
0003h
0000h
on page 295 and
Table 179
Figure
Ethernet Media Access Controller
62.
on page 295.
Product Specification
294
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