EZ80F91NA050SG Zilog, EZ80F91NA050SG Datasheet - Page 278
![IC ACCLAIM MCU 256KB 144-BGA](/photos/12/15/121558/269-144-bga_sml.jpg)
EZ80F91NA050SG
Manufacturer Part Number
EZ80F91NA050SG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3870
EZ80F91NA050SG
EZ80F91NA050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050SG
Manufacturer:
ZILOG
Quantity:
20 000
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Table 153. PLL Divider Register—High Bytes
Table 154. PLL Control Register 0 (PLL_CTL0 = 005Eh)
PS019215-0910
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:3]
[2:0]
PLL_DIV_H
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:6]
CHRP_CTL1
PLL Control Register 0
The charge pump program, lock detect sensitivity, and system clock source selections are
set using this register. A brief description of each of these PLL Control Register 0
attributes is listed below, and further listed in
Charge Pump Program (CHRP_CTL)—
current.
Lock Detect Sensitivity (LDS_CTL)—
System Clock Source (CLK_MUX)—
the external crystal oscillator (XTAL), PLL, or Real-Time Clock crystal oscillator.
Value Description
00
01
10
11
Value
00h
0h–7h
Charge pump current = 100 µA
Charge pump current = 500 µA
Charge pump current = 1.0 mA
Charge pump current = 1.5 mA
R/W
W
Description
Reserved
These bits represent the High byte of the 11 bit PLL divider
value. The complete PLL divider value is returned by
{PLL_DIV_H, PLL_DIV_L}.
7
0
7
0
R/W
W
6
0
6
0
W
R
5
0
5
0
W
R
4
0
4
0
(PLL_DIV_H = 005Dh)
Selects the system clock source from a choice of
Determines the lock criteria for the PLL.
Selects one of four values of charge pump
R/W
W
3
0
3
0
Table
R/W
154.
W
2
0
2
0
R/W
W
1
0
1
0
Product Specification
R/W
W
0
0
0
0
Phase-Locked Loop
eZ80F91 MCU
269
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