EZ80F91NA050SG Zilog, EZ80F91NA050SG Datasheet - Page 91
![IC ACCLAIM MCU 256KB 144-BGA](/photos/12/15/121558/269-144-bga_sml.jpg)
EZ80F91NA050SG
Manufacturer Part Number
EZ80F91NA050SG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3870
EZ80F91NA050SG
EZ80F91NA050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050SG
Manufacturer:
ZILOG
Quantity:
20 000
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Table 25. Motorola Bus Mode Read States (Continued)
Table 26. Motorola Bus Mode Write States
PS019215-0910
STATE S6
STATE S7
STATE S0
STATE S1
STATE S2
STATE S3
STATE S4
STATE S5
STATE S6
STATE S7
During state S6, data from the external peripheral device is driven onto the data bus.
On the rising edge of the clock entering state S7, the CPU latches data from the addressed
peripheral device and deasserts AS and DS. The peripheral device deasserts DTACK at
this time.
The Write cycle starts in S0. The CPU drives R/W High (if a preceding Write cycle leaves R/
W Low).
Entering S1, the CPU drives a valid address on the address bus.
On the rising edge of S2, the CPU asserts AS and drives R/W Low.
During S3, the data bus is driven out of the high-impedance state as the data to be written is
placed on the bus.
At the rising edge of S4, the CPU asserts DS. The CPU waits for a cycle termination signal
DTACK (WAIT). If the termination signal is not asserted at least one full CPU clock period
prior to the rising clock edge at the end of S4, the CPU inserts WAIT (T
DTACK is asserted. Each wait state is a full bus mode cycle.
During S5, no bus signals are altered.
During S6, no bus signals are altered.
On entering S7, the CPU deasserts AS and DS. As the clock rises at the end of S7, the CPU
drives R/W High. The peripheral device deasserts DTACK at this time.
The eight states for a Write operation in Motorola bus mode are listed in
Signal timing for Motorola bus mode is displayed for a Read operation in
page 83 and for a Write operation in
Motorola bus mode state is 2 CPU system clock cycles in duration.
Figure 19
on page 84. In these two figures, each
Chip Selects and Wait States
Product Specification
WAIT
Table
) states until
eZ80F91 MCU
Figure 18
26.
on
82
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