C8051T614-GQ Silicon Laboratories Inc, C8051T614-GQ Datasheet - Page 196

• Manufacturer Part Number: C8051T614-GQ
• Description: IC 8051 MCU 8K BYTE-PROG 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T61xr

Specifications of C8051T614-GQ

• Program Memory Type: OTP
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 29
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051FT610DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051T61x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1441

C8051T610/1/2/3/4/5/6/7
26.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next
match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
196
PCA0CPLn
Write to
Reset
PCA0CPHn
Write to
0
ENB
ENB
Figure 26.6. PCA High-Speed Output Mode Diagram
1
PCA
Timebase
Enable
P
W
M
1
6
n
x
C
O
M
E
n
PCA0CPLn
PCA0CPMn
C
A
P
P
n
0 0
PCA0L
C
N
A
P
n
16-bit Comparator
M
A
T
n
O
G
T
n
W
M
P
n
0 x
E
C
C
F
n
PCA0CPHn
PCA0H
Rev 1.0
Match
Toggle
C
TOGn
F
0
1
C
R
PCA0CN
0
1
C
C
F
4
CEXn
C
C
F
3
C
C
F
2
C
C
F
1
PCA Interrupt
C
C
F
0
Crossbar
Port I/O