MC908JL16CFJE Freescale Semiconductor, MC908JL16CFJE Datasheet - Page 119

• Manufacturer Part Number: MC908JL16CFJE
• Description: IC MCU 16K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL16CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: DEMO908JL16E - BOARD DEMO FOR MC908JL16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMSRW — Multi-Master Slave Read/Write
MMRXAK — Multi-Master Receive Acknowledge
MMTXBE — Multi-Master Transmit Buffer Empty
MMRXBF — Multi-Master Receive Buffer Full
8.8.5 Multi-Master IIC Data Transmit Register (MMDTR)
When the MMIIC module is enabled, MMEN = 1, data written into this register depends on whether
module is in master or slave mode.
In slave mode, the data in MMDTR will be transferred to the output circuit when:
If the calling master does not return an acknowledge bit (MMRXAK = 1), the module will release the SDA
line for master to generate a "stop" or "repeated start" condition. The data in the MMDTR will not be
Freescale Semiconductor
This bit indicates the data direction when the module is in slave mode. It is updated after the calling
address is received from a master device. MMSRW = 1 when the calling master is reading data from
the module (slave transmit mode). MMSRW = 0 when the master is writing data to the module (receive
mode).
When this bit is cleared, it indicates an acknowledge signal has been received after the completion of
8 data bits transmission on the bus. When MMRXAK is set, it indicates no acknowledge signal has
been detected at the 9th clock; the module will release the SDA line for the master to generate "stop"
or "repeated start" condition. Reset sets this bit.
This flag indicates the status of the data transmit register (MMDTR). When the CPU writes the data to
the MMDTR, the MMTXBE flag will be cleared. MMTXBE is set when MMDTR is emptied by a transfer
of its data to the output circuit. Reset sets this bit.
This flag indicates the status of the data receive register (MMDRR). When the CPU reads the data from
the MMDRR, the MMRXBF flag will be cleared. MMRXBF is set when MMDRR is full by a transfer of
data from the input circuit to the MMDRR. Reset clears this bit.
•
•
1 = Slave mode transmit
0 = Slave mode receive
1 = No acknowledge signal received at 9th clock bit
0 = Acknowledge signal received at 9th clock bit
1 = Data transmit register empty
0 = Data transmit register full
1 = Data receive register full
0 = Data receive register empty
the module detects a matched calling address (MMATCH = 1), with the calling master requesting
data (MMSRW = 1); or
the previous data in the output circuit has be transmitted and the receiving master returns an
acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0).
Address: $0044
Reset:
Read:
Write:
Figure 8-8. Multi-Master IIC Data Transmit Register (MMDTR)
MMTD7
Bit 7
1
MMTD6
6
1
MC68HC908JL16 Data Sheet, Rev. 1.1
MMTD5
5
1
MMTD4
4
1
MMTD3
3
1
MMTD2
2
1
MMTD1
1
1
Multi-Master IIC Registers
MMTD0
Bit 0
1
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