MC908JL16CFJE Freescale Semiconductor, MC908JL16CFJE Datasheet - Page 147

• Manufacturer Part Number: MC908JL16CFJE
• Description: IC MCU 16K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL16CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: DEMO908JL16E - BOARD DEMO FOR MC908JL16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 10-4
10.4.3 Port D Control Register (PDCR)
The port D control register enables/disables the pull-up resistor and slow-edge high current capability of
pins PTD6 and PTD7.
SLOWDx — Slow Edge Enable
PTDPUx — Port D Pull-up Enable Bits
10.5 Port E
Port E is a 2-bit special function port that shares its pins with the timer 2 interface module (see
Timer Interface Module
Freescale Semiconductor
The SLOWD6 and SLOWD7 bits enable the slow-edge, open-drain, high current output (25mA sink)
of port pins PTD6 and PTD7 respectively. DDRDx bit is not affected by SLOWDx.
The PTDPU6 and PTDPU7 bits enable the pull-up device on PTD6 and PTD7 respectively, regardless
the status of DDRDx bit.
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull (standard I/O)
1 = Enable pull-up device
0 = Disable pull-up device
summarizes the operation of the port D pins.
DDRD Bit
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
Address: $000A
Reset:
0
1
Read:
Write:
Bit 7
(TIM)).
PTD Bit
0
0
X
PTE0–PTE1 are available on 32-pin packages only.
X
(1)
Figure 10-13. Port D Control Register (PDCR)
= Unimplemented
6
0
0
I/O Pin Mode
Input, Hi-Z
Table 10-4. Port D Pin Functions
MC68HC908JL16 Data Sheet, Rev. 1.1
Output
5
0
0
(2)
NOTE
Accesses to DDRD
4
0
0
Read/Write
DDRD[7:0]
DDRD[7:0]
SLOWD7
3
0
SLOWD6
2
0
PTD[7:0]
Read
Pin
Accesses to PTD
PTDPU7
1
0
PTD[7:0]
PTD[7:0]
Write
PTDPU6
Bit 0
0
(3)
Chapter 6
Port E
147