MC9S08DV60ACLC Freescale Semiconductor, MC9S08DV60ACLC Datasheet - Page 242
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MC9S08DV60ACLC
Manufacturer Part Number
MC9S08DV60ACLC
Description
IC MCU 60K FLASH 3K RAM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV60ACLC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
S08DV
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
26
Operating Supply Voltage
5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
On-chip Adc
12 bit, 10 channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV60ACLC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
Section 12.3.10, “MSCAN Transmit Buffer Selection Register
when RXF flag is set (see
Write: For transmit buffers, anytime when TXEx flag is set (see
Register
Section 12.3.10, “MSCAN Transmit Buffer Selection Register
receive buffers.
Reset: Undefined (0x00XX) because of RAM-based implementation
1
2
12.4.1
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
12.4.1.1
242
The position of RTR differs between extended and standard indentifier mapping.
IDE is 0.
Register
Name
IDR0
IDR1
IDR2
IDR3
Reset:
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
W
R
Identifier Registers (IDR0–IDR3)
IDR0–IDR3 for Extended Identifier Mapping
Figure 12-24. Receive/Transmit Message Buffer — Standard Identifier Mapping
W
W
W
W
R
R
R
R
ID28
7
x
Figure 12-25. Identifier Register 0 (IDR0) — Extended Identifier Mapping
Bit 7
ID10
ID2
Section 12.3.4.1, “MSCAN Receiver Flag Register
ID27
= Unused, always read ‘x’
6
x
ID9
ID1
6
MC9S08DV60 Series Data Sheet, Rev 3
ID26
5
x
ID8
ID0
5
ID25
4
x
RTR
ID7
4
1
Section 12.3.6, “MSCAN Transmitter Flag
ID24
(CANTBSEL)”). For receive buffers, only
(CANTBSEL)”). Unimplemented for
x
3
IDE
ID6
3
2
ID23
2
x
ID5
2
(CANRFLG)”).
Freescale Semiconductor
ID22
ID4
x
1
1
ID21
Bit 0
ID3
0
x
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