MC9S08DV60ACLC Freescale Semiconductor, MC9S08DV60ACLC Datasheet - Page 61
![IC MCU 60K FLASH 3K RAM 32-LQFP](/photos/12/17/121791/mc9s08dv60aclc_sml.jpg)
MC9S08DV60ACLC
Manufacturer Part Number
MC9S08DV60ACLC
Description
IC MCU 60K FLASH 3K RAM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV60ACLC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
S08DV
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
26
Operating Supply Voltage
5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
On-chip Adc
12 bit, 10 channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV60ACLC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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4.5.10
The Flash module has seven 8-bit registers in the high-page register space and three locations in the
nonvolatile register space in Flash memory. Two of those locations are copied into two corresponding
high-page control registers at reset. There is also an 8-byte comparison key in Flash memory. Refer to
Table 4-3
registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file
normally is used to translate these names into the appropriate absolute addresses.
4.5.10.1
Bit 7 of this register is a read-only flag. Bits 6:0 may be read at any time but can be written only one time.
Before any erase or programming operations are possible, write to this register to set the frequency of the
clock for the nonvolatile memory system within acceptable limits.
Table 4-8
Freescale Semiconductor
Reset
PRDIV8
DIVLD
Field
DIV
5:0
7
6
W
R
and
shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
DIVLD
Flash Registers and Control Bits
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for Flash.
1 FCDIV has been written since reset; erase and program operations enabled for Flash.
Prescale (Divide) Flash Clock by 8 (This bit is write once.)
0 Clock input to the Flash clock divider is the bus rate clock.
1 Clock input to the Flash clock divider is the bus rate clock divided by 8.
Divisor for Flash Clock Divider — These bits are write once. The Flash clock divider divides the bus rate clock
(or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting
frequency of the internal Flash clock must fall within the range of 200 kHz to 150 kHz for proper Flash operations.
Program/Erase timing pulses are one cycle of this internal Flash clock which corresponds to a range of 5 μs to
6.7 μs. The automated programming logic uses an integer number of these pulses to complete an erase or
program operation. See
Flash Clock Divider Register (FCDIV)
0
7
Table 4-5
= Unimplemented or Reserved
PRDIV8
for the absolute address assignments for all Flash registers. This section refers to
0
6
if PRDIV8 = 1 — f
Figure 4-5. Flash Clock Divider Register (FCDIV)
if PRDIV8 = 0 — f
Table 4-7. FCDIV Register Field Descriptions
Equation 4-1
MC9S08DV60 Series Data Sheet, Rev 3
0
5
FCLK
and
FCLK
Equation
= f
0
4
= f
Bus
Description
Bus
÷ (8 × (DIV + 1))
4-2.
÷ (DIV + 1)
3
0
DIV
0
2
0
1
Chapter 4 Memory
Eqn. 4-1
Eqn. 4-2
0
0
61
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