MC9S08DV60ACLC Freescale Semiconductor, MC9S08DV60ACLC Datasheet - Page 333
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MC9S08DV60ACLC
Manufacturer Part Number
MC9S08DV60ACLC
Description
IC MCU 60K FLASH 3K RAM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV60ACLC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
S08DV
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
26
Operating Supply Voltage
5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
On-chip Adc
12 bit, 10 channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV60ACLC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The bus rate clock is the main system bus clock for the MCU. This clock source requires no
synchronization because it is the clock that is used for all internal MCU activities including operation of
the CPU and buses.
In MCUs that have no PLL and FLL or the PLL and FLL are not engaged, the fixed system clock source
is the same as the bus-rate-clock source, and it does not go through a synchronizer. When a PLL or FLL
is present and engaged, a synchronizer is required between the crystal divided-by two clock source and the
timer counter so counter transitions will be properly aligned to bus-clock transitions. A synchronizer will
be used at chip level to synchronize the crystal-related source clock to the bus clock.
The external clock source may be connected to any TPM channel pin. This clock source always has to pass
through a synchronizer to assure that counter transitions are properly aligned to bus clock transitions. The
bus-rate clock drives the synchronizer; therefore, to meet Nyquist criteria even with jitter, the frequency of
the external clock source must not be faster than the bus rate divided-by four. With ideal clocks the external
clock can be as fast as bus clock divided by four.
When the external clock source shares the TPM channel pin, this pin should not be used for other channel
timing functions. For example, it would be ambiguous to configure channel 0 for input capture when the
TPM channel 0 pin was also being used as the timer external clock source. (It is the user’s responsibility
to avoid such settings.) The TPM channel could still be used in output compare mode for software timing
functions (pin controls set not to affect the TPM channel pin).
16.4.1.2
An interrupt flag and enable are associated with the 16-bit main counter. The flag (TOF) is a
software-accessible indication that the timer counter has overflowed. The enable signal selects between
software polling (TOIE=0) where no hardware interrupt is generated, or interrupt-driven operation
(TOIE=1) where a static hardware interrupt is generated whenever the TOF flag is equal to one.
The conditions causing TOF to become set depend on whether the TPM is configured for center-aligned
PWM (CPWMS=1). In the simplest mode, there is no modulus limit and the TPM is not in CPWMS=1
mode. In this case, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000
on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus
limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When
the TPM is in center-aligned PWM mode (CPWMS=1), the TOF flag gets set as the counter changes
direction at the end of the count value set in the modulus register (that is, at the transition from the value
set in the modulus register to the next lower count value). This corresponds to the end of a PWM period
(the 0x0000 count value corresponds to the center of a period).
Freescale Semiconductor
Counter Overflow and Modulo Reset
CLKSB:CLKSA
00
01
10
11
Table 16-7. TPM Clock Source Selection
MC9S08DV60 Series Data Sheet, Rev 3
No clock selected (TPM counter disabled)
TPM Clock Source to Prescaler Input
Fixed system clock
External source
Bus rate clock
Chapter 16 Timer/PWM Module (S08TPMV3)
333
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