MC9S08DV60ACLC Freescale Semiconductor, MC9S08DV60ACLC Datasheet - Page 396
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MC9S08DV60ACLC
Manufacturer Part Number
MC9S08DV60ACLC
Description
IC MCU 60K FLASH 3K RAM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV60ACLC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
S08DV
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
26
Operating Supply Voltage
5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
On-chip Adc
12 bit, 10 channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV60ACLC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Appendix B Timer Pulse-Width Modulator (TPMV2)
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
B.2.5
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
396
CPWMS
Reset
Reset
X
0
1
W
W
R
R
Bit 15
Timer Channel Value Registers (TPMxCnVH:TPMxCnVL)
Bit 7
0
0
7
7
MSnB:MSnA
XX
XX
1X
00
01
Figure B-8. Timer Channel Value Register High (TPMxCnVH)
Figure B-9. Timer Channel Value Register Low (TPMxCnVL)
14
0
6
0
6
6
ELSnB:ELSnA
Table B-5. Mode, Edge, and Level Selection
MC9S08DV60 Series Data Sheet, Rev 3
X1
X1
00
01
10
11
00
01
10
11
10
10
13
0
5
0
5
5
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
Center-aligned
Input capture
Edge-aligned
compare
Output
12
PWM
PWM
0
4
0
Mode
4
4
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
High-true pulses (clear output on compare)
Low-true pulses (set output on compare)
High-true pulses (clear output on compare-up)
Low-true pulses (set output on compare-up)
11
3
0
3
3
0
10
0
2
0
2
2
Configuration
Freescale Semiconductor
9
0
1
0
1
1
Bit 8
Bit 0
0
0
0
0
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