MC908AP32CFAE Freescale Semiconductor, MC908AP32CFAE Datasheet - Page 105

• Manufacturer Part Number: MC908AP32CFAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 32
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt
is serviced first.
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
Freescale Semiconductor
Figure 7-11
AS MANY INTERRUPTS
AS EXIST ON CHIP
demonstrates what happens when two interrupts are pending. If an interrupt
YES
MC68HC908AP Family Data Sheet, Rev. 4
Figure 7-10. Interrupt Processing
INSTRUCTION?
INSTRUCTION?
INSTRUCTION
FROM RESET
INTERRUPT?
FETCH NEXT
INTERRUPT?
I-BIT SET?
I BIT SET?
BREAK
IRQ1
SWI
RTI
NO
NO
NO
NO
NO
YES
YES
YES
YES
LOAD PC WITH INTERRUPT VECTOR
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
STACK CPU REGISTERS
SET I-BIT
Exception Control
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