MC908AP32CFAE Freescale Semiconductor, MC908AP32CFAE Datasheet - Page 173

• Manufacturer Part Number: MC908AP32CFAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 32
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.8.3 SCI Control Register 3
SCI control register 3:
R8 — Received Bit 8
T8 — Transmitted Bit 8
DMARE — DMA Receive Enable Bit
DMATE — DMA Transfer Enable Bit
ORIE — Receiver Overrun Interrupt Enable Bit
Freescale Semiconductor
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When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received
character. R8 is received at the same time that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect
on the R8 bit.
When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR.
1 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI
0 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI
1 = SCTE DMA service requests enabled; SCTE CPU interrupt requests disabled
0 = SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted
Enables these interrupts:
–
–
–
Parity error interrupts
Receiver overrun interrupts
Noise error interrupts
Framing error interrupts
receiver CPU interrupt requests enabled)
receiver CPU interrupt requests enabled)
Address:
The DMA module is not included on this MCU. Writing a logic 1 to DMARE
or DMATE may adversely affect MCU performance.
The DMA module is not included on this MCU. Writing a logic 1 to DMARE
or DMATE may adversely affect MCU performance.
Reset:
Read:
Write:
$0015
Bit 7
R8
U
Figure 11-11. SCI Control Register 3 (SCC3)
= Unimplemented
T8
U
6
MC68HC908AP Family Data Sheet, Rev. 4
DMARE
5
0
CAUTION
CAUTION
DMATE
4
0
U = Unaffected
ORIE
3
0
NEIE
2
0
FEIE
1
0
PEIE
Bit 0
0
I/O Registers
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