M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 170

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
1
e
E
Figure 13.13 Counter Increment/Decrement Mode
. v
6
J
Figure 13.12 Counter Increment Mode
0
C
2
9
2 /
0 .
B
8
0
0
0
IT=0 in the G1BCR0 register
(Base timer interrupt generated
by the bit 15 overflow)
IT=1 in the G1BCR0 register
(Base timer interrupt generated
by the bit 14 overflow)
G
4
J
The above applies to the following conditions.
7
a
o r
The RST4 bit in the G1BCR0 register is set to "0" (the base timer is not reset by matching the G1BTRR register)
The RST1 bit in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register)
The UD1 to UD0 bits in the G1BCR1 register are set to "00
0 -
. n
IT=0 in the G1BCR0 register
(Base timer interrupt generated
by the bit 15 overflow)
u
IT=1 in the G1BCR0 register
(Base timer interrupt generated
by the bit 14 overflow)
2
p
3
0
, 1
0
(
M
2
1
0
0
6
State of a counter
7
C
b14 overflow signal
Base Timer interrupts
b15 overflow signal
Base Timer interrupt
2 /
page 148
, 8
State of a counter
M
b14 overflow signal
Base Timer interrupts
b15 overflow signal
Base Timer interrupt
1
6
C
2 /
f o
8
3
FFFF
C000
4000
8000
0000
) B
8
5
"1"
"1"
"0"
"0"
16
16
16
16
16
FFFF
C000
8000
4000
0000
16
16
16
16
16
"1"
"1"
"0"
"0"
2
" (counter increment mode)
13. Timer S