M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 71

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
e
E
1
. v
Figure 7.6 PCLKR Register and PM2 Register
J
6
0
C
2
9
0 .
2 /
B
0
0
8
0
4
G
J
NOTE:
Peripheral Clock Select Register
7
a
0 0 0
b7
o r
Processeor Mode Register 2
0 -
. n
b7
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).
u
2
b6
3
p
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).
2. The PM20 bit become effective when PLC07 bit in the PLC0 register is set to "1" (PLL on). Change the PM20 bit
3. Once this bit is set to “1”, it cannot be set to “0” by program.
4. Writing to the following bits has no effect when the PM21 bit is set to “1”:
5. Setting the PM22 bit to “1” results in the following conditions:
6. For NMI function, the PM24 bit must be set to “1”(NMI function). Once this bit is set to “1”, it cannot be cleared to
7. SD input is valid regardless of the PM24 setting.
b6
0
, 1
0
(
when the PLC07 bit is set to "0" (PLL off). Set the PM20 bit to "0" (2 waits) when PLL clock > 16 MHz.
“0” by program.
b5
- The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or
- The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count
- The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
- The watchdog timer does not stop in wait mode.
M
When the PM21 bit is set to "1", do not execute the WAIT instruction.
b5
2
PLL clock) (system clock of count source selected by the CM21 bit is valid)
source.
entered)
0
1
b4
0 0 0
CM02 bit in the CM0 register
CM05 bit in the CM0 register (main clock is not halted)
CM07 bit in the CM0 register (CPU clock source does not change)
CM10 bit in the CM1 register (stop mode is not entered)
CM11 bit in the CM1 register (CPU clock source does not change)
CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in the PLC0 register (PLL frequency synthesizer setting do not change)
0
b4
6
7
C
b3
0
b3
2 /
b2
, 8
page 49
b2
b1
M
b1
1
b0
6
b0
C
f o
2 /
Bit Symbol
Bit Symbol
(b7-b2)
PCLK0
PCLK1
8
(b7-b5)
PM20
PM21
PM22
PM24
3
Symbol
PCLKR
) B
(b3)
8
Symbol
PM2
5
(1)
Specifying wait when
accessing SFR during PLL
operation
System clock protective bit
WDT count source
protective bit
Reserved bit
P85/NMI configuration bit
Nothing is assigned. When write, set to“0”.
When read,its content is indeterminate
Timers A, B clock select bit
(Clock source for Timers A,
B, Timer S, the dead time
timer, SI/O3, SI/O4,multi-
master I 2 C bus)
SI/O clock select bit (Clock
source for UART0 to
UART2)
Reserved bit
(1)
(2)
Bit Name
Bit Name
Address
025E
(3,5)
Address
001E
16
16
(6,7)
(3,4)
After Reset
XXX00000
After Reset
00000011
0: f
1: f
Set to “0”
0: f
1: f
0: 2 wait
1: 1 wait
0: Clock is protected by PRCR
1: Clock modification disabled
0: CPU clock is used for the
1: On-chip oscillator clock is used
Set to “0”
0: P8
1: NMI function
register
watchdog timer count source
for the watchdog timer count
source
2
1
2SIO
1SIO
5
function (NMI disable)
2
2
Function
Function
7. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW