M30625FGPGP#U5C Renesas Electronics America, M30625FGPGP#U5C Datasheet - Page 136
M30625FGPGP#U5C
Manufacturer Part Number
M30625FGPGP#U5C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 12.10
12.5.10 Interrupt Priority Level Select Circuit
The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt
requests are sampled at the same sampling point.
Figure 12.10 shows the Interrupts Priority Select Circuit.
Jan 10, 2006
Priority level of each interrupt
Timer B4, UART1 bus collision
Timer B3, UART0 bus collision
UART1 transmission, NACK1
UART0 transmission, NACK0
UART2 transmission, NACK2
UART1 reception, ACK1
UART0 reception, ACK0
UART2 reception, ACK2
re-oscillation detection
Low voltage detection
Oscillation stop and
UART 2 bus collision
Key input interrupt
Watchdog timer
Address match
A/D conversion
SI/O4, INT5
Interrupts Priority Select Circuit
Timer A1
Timer B1
Timer A4
Timer A2
Timer A0
SI/O, INT4
Timer B2
Timer B0
Timer A3
Timer B5
DMA1
DMA0
INT3
INT2
INT0
I flag
DBC
INT1
NMI
IPL
Page 119 of 390
Level 0 (initial value)
Priority of peripheral function interrupts
(if priority levels are same)
Lowest
Highest
Interrupt request level resolution output to clock
generating circuit (Figure 10.1 Clock Generation Circuit)
Interrupt request
accepted
12. Interrupt
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