M30625FGPGP#U5C Renesas Electronics America, M30625FGPGP#U5C Datasheet - Page 228
M30625FGPGP#U5C
Manufacturer Part Number
M30625FGPGP#U5C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.27
17.1.3.1
17.1.3.2
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low
while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when the SDAi
pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vector, check the
BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt.
A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2) to “1” (start).
A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to “1” (start).
A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to “1” (start).
The output procedure is described below.
The function of the STSPSEL bit is shown in Table 17.14 and Figure 17.28.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
(2) Set the STSPSEL bit in the UiSMR4 register to “1” (output).
Jan 10, 2006
i = 0 to 2
NOTES :
3 to 6 cycles < duration for setting-up
3 to 6 cycles < duration for holding
(Start condition)
(Stop condition)
Detection of Start and Stop Condition
Detection of Start and Stop Condition
Output of Start and Stop Condition
1. When the PCLK1 bit in the PCLKR register = 1, this is the cycle number of
SDA i
SDAi
SCLi
f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO.
Page 211 of 390
Duration for
setting up
(1)
(1)
Duration for
holding
17. Serial Interface
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