M30625FGPGP#U5C Renesas Electronics America, M30625FGPGP#U5C Datasheet - Page 197
M30625FGPGP#U5C
Manufacturer Part Number
M30625FGPGP#U5C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.4
RXDi
i=0 to 2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register
UiERE: Bit in UiC1 register
SP
SP
Jan 10, 2006
reverse circuit
SP
RXD data
STPS
1SP
2SP
0
1
STPS
UARTi Transmit/Receive Unit
2SP
1SP
0
1
0
SP
0
PAR
0
1
PAR
IOPOL
Page 180 of 390
No reverse
Reverse
PRYE
PAR
enabled
PAR enabled
0
PAR
disabled
0
1
1
PRYE
0
PAR
disabled
0
SMD2 to SMD0
UART
SMD2 to SMD0
Clock
synchronous
type
0
UART
Clock
synchronous
type
1
1
0
0
0
UART
(9 bits)
UART
(9 bits)
0
UART
(7 bits)
UART
(8 bits)
1
0
Clock
synchronous type
1
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
0
D8
Data bus high-order bits
D8
Data bus low-order bits
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
Clock
synchronous type
UART
(8 bits)
UART
(9 bits)
1
UART(7 bits)
0
0
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6
UART(7 bits)
Logic reverse circuit + MSB/LSB conversion circuit
Logic reverse circuit + MSB/LSB conversion circuit
UiERE
Error signal output
enable
Error signal output
disable
0
1
output circuit
D5 D4 D3
Error signal
UARTi receive register
UARTi transmit register
IOPOL
0
1
Reverse
D2 D1 D0
No reverse
reverse circuit
TXD data
17. Serial Interface
UiRB register
UiTB register
TXDi
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