M30625FGPGP#U5C Renesas Electronics America, M30625FGPGP#U5C Datasheet - Page 77
M30625FGPGP#U5C
Manufacturer Part Number
M30625FGPGP#U5C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
8.2
8.2.1
Table 8.2
NOTES:
8.2.2
8.2.3
PM11=1
PM06=1
PM11=0
PM06=1
PM11=0
PM06=0
The following describes the signals needed for accessing external devices and the functionality of software wait.
1. No values other than those shown above can be set.
Set Value
The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or 20 bits by
using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 8.2 shows the PM06 and
PM11 Bits Set Value and Address Bus Width.
When processor mode is changed from single-chip mode to memory extension mode, the address bus is
indeterminate until any external area is accessed.
When input on the BYTE pin is high (data bus is 8 bits wide), 8 lines D0 to D7 comprise the data bus; when
input on the BYTE pin is low(data bus is 16 bits wide), 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
The chip select (hereafter referred to as the CSi) signals are output from the CSi (i = 0 to 3) pins. These pins
can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 8.1 shows the CSR Register.
During 1-Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output from the
CSi pin. During 4-Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to 9. Memory
Space Expansion Function. Figure 8.2 shows the Example of Address Bus and CSi Signal Output in 1-Mbyte
mode.
Bus Control
Jan 10, 2006
Address Bus
Data Bus
Chip Select Signal
PM06 and PM11 Bits Set Value and Address Bus Width
(1)
P3_4 to P3_7
P4_0 to P4_3
A12 to A15
P4_0 to P4_3
A12 to A15
A16 to A19
Page 60 of 390
Pin Function
12 bits
16 bits
20 bits
Address Bus Width
8. Bus
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