M30625FGPGP#U5C Renesas Electronics America, M30625FGPGP#U5C Datasheet - Page 238
M30625FGPGP#U5C
Manufacturer Part Number
M30625FGPGP#U5C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.33
This diagram applies to the case where IOPOL=1 (reversed).
(1) The ABSCS Bit in the UiSMR Register (Bus collision detect sampling clock select)
(2) The ACSE Bit in the UiSMR Register (Auto clear of transmit enable bit)
(3) The SSS Bit in the UiSMR Register (Transmit start condition select)
Transfer clock
Transfer clock
TXDi
RXDi
Timer Aj
Transfer clock
TXDi
RXDi
IR bit in UiBCNIC
register
TE bit in UiC1
register
TXDi
CLKi
TXDi
RXDi
Timer Aj: Timer A3 when UART0; Timer A4 when UART1; Timer A0 when UART2
NOTES :
NOTES :
Jan 10, 2006
1. BCNIC register when UART2.
If SSS bit = 0, the serial interface starts sending data one transfer clock cycle after the transmission enable condition is met.
If SSS bit = 1, the serial interface starts sending data at the rising edge
1. The falling edge of RXDi when IOPOL=0; the rising edge of RXDi when IOPOL =1.
2. The transmit condition must be met before the falling edge
(1)
Bus Collision Detect Function-Related Bits
Transmission enable condition is met
Page 221 of 390
(NOTE 2)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
ST
Trigger signal is applied to the TAjIN pin
ST
ST
ST
D0
D0
D0
D0
D1
D1
D1
D1
D2
D2
D2
D2
(1)
D3
D3
of RXD.
D3
D3
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
D4
D4
(1)
of RXDi
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
If ACSE bit = 1 (automatically
clear when bus collision occurs), the
TE bit is cleared to “0”
(transmission disabled) when the
IR bit in the UiBCNIC register= 1
(unmatching detected).
D7
D7
D7
D7
D8
D8
D8
D8
17. Serial Interface
SP
SP
SP
SP
(i=0 to 2)
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