HD64F7045F28V Renesas Electronics America, HD64F7045F28V Datasheet - Page 205

IC SH2 MCU FLASH 144QFP

HD64F7045F28V

Manufacturer Part Number
HD64F7045F28V
Description
IC SH2 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheets

Specifications of HD64F7045F28V

Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7045F28V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7045F28V
Manufacturer:
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Quantity:
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6.1.31
Description: Does signed multiplication of 32-bit operands obtained using the contents of general
registers Rm and Rn as addresses. The 64-bit result is added to contents of the MAC register, and
the final result is stored in the MAC register. Every time an operand is read, they increment Rm
and Rn by four.
When the S bit is cleared to 0, the 64-bit result is stored in the coupled MACH and MACL
registers. When bit S is set to 1, addition to the MAC register is a saturation operation of 48 bits
starting from the LSB. For the saturation operation, only the lower 48 bits of the MACL register
are enabled and the result is limited to a range of H'FFFF800000000000 (minimum) and
H'00007FFFFFFFFFFF (maximum).
Operation:
Format
MAC.L @Rm+,
MACL(long m,long n) /* MAC.L @Rm+,@Rn+*/
{
unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;
unsigned long temp0,templ,temp2,temp3;
long tempm,tempn,fnLmL;
tempn=(long)Read_Long(R[n]);
R[n]+=4;
tempm=(long)Read_Long(R[m]);
R[m]+=4;
if ((long)(tempn^tempm)<0) fnLmL=-1;
else fnLmL=0;
if (tempn<0) tempn=0-tempn;
if (tempm<0) tempm=0-tempm;
@Rn+
MAC.L (Multiply and Accumulate Calculation Long): Arithmetic Instruction
Abstract
Signed operation,
(Rn)
MAC
(Rm) + MAC
Code
0000nnnnmmmm1111 3/(2
Rev. 5.00 Jun 30, 2004 page 189 of 512
Cycle T Bit SH-1 SH-2
to 4)
Section 6 Instruction Descriptions
REJ09B0171-0500O
Instructions
Applicable
SH-
DSP

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