HD64F7045F28V Renesas Electronics America, HD64F7045F28V Datasheet - Page 504

IC SH2 MCU FLASH 144QFP

HD64F7045F28V

Manufacturer Part Number
HD64F7045F28V
Description
IC SH2 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheets

Specifications of HD64F7045F28V

Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7045F28V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7045F28V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 7 Pipeline Operation
Delayed Conditional Branch Instructions (SH-2 CPU, SH-DSP): Include the following
instruction types:
The pipeline has three stages: IF, ID, and EX. Condition verification is performed in the ID stage.
1. When condition is satisfied
2. When condition is not satisfied
Rev. 5.00 Jun 30, 2004 page 488 of 512
REJ09B0171-0500O
BF/S label
BT/Slabel
The branch destination address is calculated in the EX stage. The instruction after the
conditional branch instruction (instruction A) is fetched and executed, but the instruction after
that is fetched and discarded. The branch destination instruction begins its fetch from the slot
following the slot which has the EX stage of instruction A (figure 7.80).
If it is determined that a condition is not satisfied at the ID stage, the EX stage proceeds
without doing anything. The next instruction also executes a fetch (figure 7.81).
Third instruction in series
Third instruction in series
Branch destination
Figure 7.81 Branch Instruction when Condition Is Not Satisfied
Figure 7.80 Branch Instruction when Condition Is Satisfied
Next instruction
Next instruction
Instruction A
Instruction A
.....
.....
.....
IF
IF
ID
ID
IF
IF
EX
EX
ID
IF
IF
EX
ID
ID
IF
IF
EX MA WB
.....
ID
EX
ID
IF
(Fetched but discarded)
EX
EX
.....
ID
EX
.....
.....
.....
: Slot
: Slot

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