PIC12F519-I/P Microchip Technology, PIC12F519-I/P Datasheet - Page 21
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PIC12F519-I/P
Manufacturer Part Number
PIC12F519-I/P
Description
IC PIC MCU FLASH 1KX12 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F519-ISN.pdf
(96 pages)
2.PIC12F519-ISN.pdf
(4 pages)
3.PIC12F519-ISN.pdf
(22 pages)
4.PIC12F519-IP.pdf
(88 pages)
Specifications of PIC12F519-I/P
Program Memory Type
FLASH
Program Memory Size
1.5KB (1K x 12)
Package / Case
8-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Peripherals
POR, WDT
Number Of I /o
5
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
41 B
Interface Type
USB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
Package
8PDIP
Device Core
PIC
Family Name
PIC12
Maximum Speed
8 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162096 - HEADER MPLAB ICD2 PIC16F526 8/14AC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F519-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
4.6
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits <8:0> of the PC are pro-
vided by the GOTO instruction word. The Program
Counter (PCL) is mapped to PC<7:0>. Bit 5 of the STA-
TUS register provides page information to bit 9 of the
PC (Figure 4-3).
For a CALL instruction, or any instruction where the
PCL is the destination, bits <7:0> of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-3).
Instructions where the PCL is the destination, or modify
PCL instructions, include MOVWF PC, ADDWF PC and
BSF PC,5.
FIGURE 4-3:
© 2007 Microchip Technology Inc.
CALL or Modify PCL Instruction
GOTO Instruction
Note:
Program Counter
PC
PC
Because PC<8> is cleared in the CALL
instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
7
7
10
10
9
Status
9
Status
PA0
Reset to ‘0’
PA0
8 7
8 7
LOADING OF PC
BRANCH INSTRUCTIONS
Instruction Word
Instruction Word
PCL
PCL
0
0
0
0
Preliminary
4.6.1
The PC is set upon a Reset, which means that the PC
addresses the last location in the last page (i.e., the
oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 00h and
begin executing user code.
The STATUS register page preselect bits are cleared
upon a Reset, which means that page 0 is pre-selected.
Therefore, upon a Reset, a
automatically cause the program to jump to page 0 until
the value of the page bits is altered.
4.7
The PIC12F519 device has a two-deep, 12-bit wide
hardware PUSH/POP stack.
A CALL instruction will PUSH the current value of Stack
1 into Stack 2 and then PUSH the current PC value,
incremented by one, into Stack Level 1. If more than two
sequential CALLs are executed, only the most recent two
return addresses are stored.
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into Stack Level 1. If more than two sequential
RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2. Note that
the W register will be loaded with the literal value
specified in the instruction. This is particularly useful for
the implementation of data look-up tables within the
program memory.
Note 1: There are no Status bits to indicate stack
2: There are no instruction mnemonics
Stack
EFFECTS OF RESET
overflows or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLW instructions.
PIC12F519
GOTO instruction will
DS41319A-page 19