PIC12F519-I/P Microchip Technology, PIC12F519-I/P Datasheet - Page 24

• Manufacturer Part Number: PIC12F519-I/P
• Description: IC PIC MCU FLASH 1KX12 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F519-I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.5KB (1K x 12)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Ram Size: 41 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 41 B
• Interface Type: USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• Package: 8PDIP
• Device Core: PIC
• Family Name: PIC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162096 - HEADER MPLAB ICD2 PIC16F526 8/14AC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F519
REGISTER 5-2:
REGISTER 5-3:
DS41319A-page 22
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
bit 7
Legend:
S = Bit can only be set
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
U-0
—
—
Unimplemented: Do not use
EEADR<5:0>: 6-bits of address to be read from/written to data Flash
Unimplemented: Do not use
FREE: Flash Data Memory Row Erase Enable Bit
1 = Program memory row being pointed to by EEADR will be erased on the next write cycle. No write
0 = Perform write only
WRERR: Write Error Flag bit
1 = A write operation terminated prematurely (by device Reset)
0 = Write operation completed successfully
WREN: Write Enable bit
1 = Allows write cycle to Flash data memory
0 = Inhibits write cycle to Flash data memory
WR: Write Control bit
1 = Initiate a erase or write cycle
0 = Write/Erase cycle is complete
RD: Read Control bit
1 = Initiate a read of Flash data memory
0 = Do not read Flash data memory
U-0
U-0
—
—
will be performed. This bit is cleared at the completion of the erase operation.
EEADR: FLASH ADDRESS REGISTER
EECON: FLASH CONTROL REGISTER
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
EEADR5
R/W-x
U-0
—
EEADR4
R/W-0
R/W-x
FREE
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EEADR3
WRERR
R/W-x
R/W-0
EEADR2
WREN
R/W-0
R/W-x
© 2007 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
EEADR1
R/W-x
R/W-0
WR
EEADR0
R/W-0
R/W-x
RD
bit 0
bit 0