PIC18F2431-I/SP Microchip Technology, PIC18F2431-I/SP Datasheet - Page 162
![IC PIC MCU FLASH 8KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2431-I/SP
Manufacturer Part Number
PIC18F2431-I/SP
Description
IC PIC MCU FLASH 8KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
8.PIC18F2431-ISP.pdf
(396 pages)
Specifications of PIC18F2431-I/SP
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164035 - MODULE SKT FOR 18F2X31 28SOICDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2431-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18F2431-ISP PDF datasheet #8
- Current page: 162 of 392
- Download datasheet (4Mb)
PIC18F2331/2431/4331/4431
17.2.1
The QEI module shares its input pins with the Input
Capture (IC) module. The inputs are mutually
exclusive; only the IC module or the QEI module (but
not both) can be enabled at one time. Also, because
the IC and QEI are multiplexed to the same input pins,
the programmable noise filters can be dedicated to one
module only.
REGISTER 17-2:
DS39616D-page 162
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4-2
bit 1-0
Note 1:
R/W-0
VELM
2:
3:
4:
QEI must be enabled and in Index mode.
QEI mode select must be cleared (= 000) to enable CAP1, CAP2 or CAP3 inputs. If QEI and IC modules
are both enabled, QEI will take precedence.
Enabling one of the QEI operating modes remaps the IC Buffer registers, CAP1BUFH, CAP1BUFL,
CAP2BUFH, CAP2BUFL, CAP3BUFH and CAP3BUFL, as the VELRH, VELRL, POSCNTH, POSCNTL,
MAXCNTH and MAXCNTL registers (respectively) for the QEI.
The QERR bit must be cleared in software.
QEI CONFIGURATION
VELM: Velocity Mode bit
1 = Velocity mode disabled
0 = Velocity mode enabled
QERR: QEI Error bit
1 = Position counter overflow or underflow
0 = No overflow or underflow
UP/DOWN: Direction of Rotation Status bit
1 = Forward
0 = Reverse
QEIM<2:0>: QEI Mode bits
111 = Unused
110 = QEI enabled in 4x Update mode; position counter is reset on period match (POSCNT = MAXCNT)
101 = QEI enabled in 4x Update mode; INDX resets the position counter
100 = Unused
010 = QEI enabled in 2x Update mode; position counter is reset on period match (POSCNT = MAXCNT)
001 = QEI enabled in 2x Update mode; INDX resets the position counter
000 = QEI off
PDEC<1:0>: Velocity Pulse Reduction Ratio bits
11 = 1:64
10 = 1:16
01 = 1:4
00 = 1:1
QERR
R/W-0
QEICON: QUADRATURE ENCODER INTERFACE CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
UP/DOWN
R-0
(1)
(2,3)
QEIM2
R/W-0
(2,3)
(4)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
QEIM1
R/W-0
The operation of the QEI is controlled by the QEICON
Configuration register (see
Note:
(2,3)
In the event that both QEI and IC are
enabled, QEI will take precedence and IC
will remain disabled.
QEIM0
R/W-0
(2,3)
2010 Microchip Technology Inc.
x = Bit is unknown
Register
PDEC1
R/W-0
17-2).
PDEC0
R/W-0
bit 0
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