PIC18F2431-I/SP Microchip Technology, PIC18F2431-I/SP Datasheet - Page 216
![IC PIC MCU FLASH 8KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2431-I/SP
Manufacturer Part Number
PIC18F2431-I/SP
Description
IC PIC MCU FLASH 8KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
8.PIC18F2431-ISP.pdf
(396 pages)
Specifications of PIC18F2431-I/SP
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164035 - MODULE SKT FOR 18F2X31 28SOICDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2431-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18F2431-ISP PDF datasheet #8
- Current page: 216 of 392
- Download datasheet (4Mb)
PIC18F2331/2431/4331/4431
19.3.2
Master mode of operation is supported in firmware
using interrupt generation on the detection of the Start
and Stop conditions. The Stop (P) and Start (S) bits are
cleared from a Reset or when the SSP module is
disabled. The Stop (P) and Start (S) bits will toggle
based on the Start and Stop conditions. Control of the
I
is Idle and both the S and P bits are clear.
In Master mode, the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<5:4> or
TRISD<3:2> bits. The output level is always low,
regardless of the value(s) in PORTC<5:4> or
PORTD<3:2>. So when transmitting data, a ‘1’ data bit
must have the TRISC<4> bit set (input) and a ‘0’ data
bit must have the TRISC<4> bit cleared (output). The
same scenario is true for the SCL line with the
TRISC<4> or TRISD<2> bit. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt will occur if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode Idle (SSPM<3:0> = 1011) or with the
Slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 19-3:
DS39616D-page 216
INTCON
PIR1
PIE1
SSPBUF
SSPADD
SSPCON
SSPSTAT
TRISC
TRISD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the SSP module in I
Note 1:
2
C bus may be taken when the P bit is set, or the bus
Name
2:
(2)
(2)
Maintain these bits clear in I
Depending upon the setting of SSPMX in CONFIG3H, these pins are multiplexed to PORTC or PORTD.
MASTER MODE
SSP Receive Buffer/Transmit Register
SSP Address Register (I
PORTC Data Direction Register
PORTD Data Direction Register
GIE/GIEH
SMP
WCOL
2
Bit 7
C module.
REGISTERS ASSOCIATED WITH I
—
—
(1)
PEIE/GIEL
SSPOV
CKE
ADIF
ADIE
Bit 6
(1)
2
2
C mode)
C mode.
TMR0IE
SSPEN
RCIE
RCIF
Bit 5
D/A
INT0IE
Bit 4
TXIF
TXIE
CKP
P
2
C™ OPERATION
SSPM3
SSPIF
SSPIE
RBIE
Bit 3
19.3.3
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the SSP
module is disabled. The Stop (P) and Start (S) bits will
toggle based on the Start and Stop conditions. Control
of the I
is set, or the bus is Idle and both the S and P bits clear.
When the bus is busy, enabling the SSP interrupt will
generate the interrupt when the Stop condition occurs.
In Multi-Master mode, the SDA line must be monitored
to see if the signal level is the expected output level.
This check only needs to be done when a high level is
output. If a high level is expected and a low level is
present, the device needs to release the SDA and SCL
lines (set TRISC<5:4> or TRISD<3:2>). There are two
stages where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address
transfer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to retransfer the data at a
later time.
S
2
C bus may be taken when bit P (SSPSTAT<4>)
TMR0IF
CCP1IE
CCP1IF
SSPM2
Bit 2
R/W
MULTI-MASTER MODE
TMR2IF
TMR2IE
SSPM1
INT0IF
Bit 1
UA
2010 Microchip Technology Inc.
TMR1IF
TMR1IE
SSPM0
2
RBIF
Bit 0
C mode.
BF
Reset Values
on Page:
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