PIC18F2431-I/SP Microchip Technology, PIC18F2431-I/SP Datasheet - Page 187
![IC PIC MCU FLASH 8KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2431-I/SP
Manufacturer Part Number
PIC18F2431-I/SP
Description
IC PIC MCU FLASH 8KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
8.PIC18F2431-ISP.pdf
(396 pages)
Specifications of PIC18F2431-I/SP
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164035 - MODULE SKT FOR 18F2X31 28SOICDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2431-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18F2431-ISP PDF datasheet #8
- Current page: 187 of 392
- Download datasheet (4Mb)
18.6
PWM duty cycle is defined by the PDCx (PDCxL and
PDCxH) registers. There are a total of four PWM Duty
Cycle registers for four pairs of PWM channels. The
Duty Cycle registers have 14-bit resolution by combin-
ing six LSbs of PDCxH with the 8 bits of PDCxL. PDCx
is a double-buffered register used to set the counting
period for the PWM time base.
18.6.1
There are four 14-bit Special Function Registers used
to specify duty cycle values for the PWM module:
• PDC0 (PDC0L and PDC0H)
• PDC1 (PDC1L and PDC1H)
• PDC2 (PDC2L and PDC2H)
• PDC3 (PDC3L and PDC3H)
FIGURE 18-11:
2010 Microchip Technology Inc.
PTMR<11:0>
PDCx<13:0>
Note 1: This value is decoded from the Q clocks:
PWM Duty Cycle
PWM DUTY CYCLE REGISTERS
00 = duty cycle match occurs on Q1
01 = duty cycle match occurs on Q2
10 = duty cycle match occurs on Q3
11 = duty cycle match occurs on Q4
DUTY CYCLE COMPARISON
Unused
Unused
PTMRH<7:0>
PTMRH<3:0>
PDCxH<7:0>
PIC18F2331/2431/4331/4431
PDCxH<5:0>
The value in each Duty Cycle register determines the
amount of time that the PWM output is in the active
state. The upper 12 bits of PDCx holds the actual duty
cycle value from PTMRH/L<11:0>, while the lower
2 bits control which internal Q clock the duty cycle
match will occur. This 2-bit value is decoded from the Q
clocks as shown in
1:1 or PTCKPS<1:0> = 00).
In Edge-Aligned mode, the PWM period starts at Q1
and ends when the Duty Cycle register matches the
PTMR register as follows. The duty cycle match is con-
sidered when the upper 12 bits of the PDCx are equal
to the PTMR and the lower 2 bits are equal to Q1, Q2,
Q3 or Q4, depending on the lower two bits of the PDCx
(when the prescaler is 1:1 or PTCKPS<1:0> = 00)
Each compare unit has logic that allows override of the
PWM signals. This logic also ensures that the PWM
signals will complement each other (with dead-time
insertion) in Complementary mode (see
“Dead-Time
Note:
Comparator
PTMRL<7:0>
PTMRL<7:0>
When
(PTCKPS<1:0> ~00), the duty cycle
match occurs at the Q1 clock of the
instruction cycle when the PTMR and
PDCx match occurs.
Generators”).
Figure 18-11
the
PDCxL<7:0>
PDCxL<7:0>
prescaler
(when the prescaler is
DS39616D-page 187
is
Q Clocks
Section 18.7
<1:0>
not
(1)
.
1:1
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