ATMEGA169L-8MI Atmel, ATMEGA169L-8MI Datasheet
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATMEGA169L-8MI
Specifications of ATMEGA169L-8MI
ATMEGA169L-4MI
Related parts for ATMEGA169L-8MI
ATMEGA169L-8MI Summary of contents
Page 1
... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad MLF • Operating Voltage: – 1.8 - 5.5V for ATmega169V – 2.7 - 5.5V for ATmega169L – 4.5 - 5.5V for ATmega169 • Temperature range: – -40°C to 85°C Industrial ® 8-Bit Microcontroller ...
Page 2
... Features (Continued) • Speed Grade: – MHz for ATmega169V – MHz for ATmega169L – MHz for ATmega169 • Ultra-Low Power Consumption – Active Mode: 1 MHz, 1.8V: 400µA 32 kHz, 1.8V: 20µA (including Oscillator) 32 kHz, 1.8V: 40µA (including Oscillator and LCD) – Power-down Mode: 0.5µ ...
Page 3
Overview The ATmega169 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize ...
Page 4
... Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega169 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications ...
Page 5
Pin Descriptions VCC Digital supply voltage. GND Ground. Port A (PA7..PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink ...
Page 6
As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset ...
Page 7
AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and ...
Page 8
Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling ...
Page 9
Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after ...
Page 10
Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc- tion Set Description” for detailed information. General Purpose The Register File is optimized for the AVR Enhanced ...
Page 11
The X-register, Y-register, and The registers R26..R31 have some added functions to their general purpose usage. Z-register These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are ...
Page 12
Instruction Execution This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk Timing source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction ...
Page 13
Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 252. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. ...
Page 14
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock ...
Page 15
AVR ATmega169 This section describes the different memories in the ATmega169. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In Memories addition, the ATmega169 features an EEPROM Memory for data storage. All ...
Page 16
SRAM Data Memory Figure 9 shows how the ATmega169 SRAM Memory is organized. The ATmega169 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT ...
Page 17
Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk 10. Figure 10. On-chip Data SRAM Access Cycles EEPROM Data Memory The ATmega169 contains ...
Page 18
The EEPROM Address Register – EEARH and EEARL • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega169 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers ...
Page 19
Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the ...
Page 20
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling inter- rupts globally) so that no interrupts will occur during execution of these functions. ...
Page 21
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. EEPROM Write During Power- When entering Power-down sleep mode ...
Page 22
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an ...
Page 23
System Clock and Clock Options Clock Systems and their Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, ...
Page 24
ADC Clock – clk The ADC is provided with a dedicated clock domain. This allows halting the CPU and ADC I/O clocks in order to reduce noise generated by digital circuitry. This gives more accu- rate ADC conversion results. Clock ...
Page 25
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 12. Either a quartz crystal or a ceramic resonator may be used. ...
Page 26
Table 5. Start-up Times for the Crystal Oscillator Clock Selection Notes: Low-frequency Crystal To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency Oscillator crystal Oscillator must be selected by setting the CKSEL Fuses ...
Page 27
Table 7. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Note: Calibrated Internal RC The calibrated internal RC Oscillator provides a fixed 8.0 MHz clock. The frequency is nominal value at 3V and MHz frequency ...
Page 28
Oscillator Calibration Register – OSCCAL • Bits 6..0 – CAL6..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove pro- cess variations from the Oscillator frequency. This is done automatically during Chip ...
Page 29
External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 13. To run the device on an external clock, the CKSEL Fuses must be pro- grammed to “0000”. Figure 13. External ...
Page 30
Timer/Counter Oscillator ATmega169 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when the calibrated internal RC Oscillator is selected as system clock source. The Oscillator is ...
Page 31
The device is shipped with the CKDIV8 Fuse programmed. Table 13. Clock Prescaler Select Switching Time When switching between prescaler settings, the System Clock Prescaler ensures ...
Page 32
Power Management Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the and Sleep Modes power consumption to the application’s requirements. To ...
Page 33
Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system to ...
Page 34
The LCD controller and Timer/Counter2 can be clocked both synchronously and asyn- chronously in Power-save mode. The clock source for the two modules can be selected independent of each other. If neither the LCD controller nor the Timer/Counter2 is using ...
Page 35
Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume ...
Page 36
System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts exe- cution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – ...
Page 37
Figure 14. Reset Logic Table 16. Reset Characteristics Notes: 2514H–AVR–05/03 Power-on Reset Circuit Brown-out BODLEVEL [2..0] Reset Circuit Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CKSEL[3:0] SUT[1:0] Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT ...
Page 38
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 16. The POR is activated whenever V detection level. The POR circuit can be used to trigger the ...
Page 39
... V production test. This guarantees that a Brown-Out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed BODLEVEL = 101 for ATmega169L. Symbol Parameter V Brown-out Detector Hysteresis HYST t ...
Page 40
When the BOD is enabled, and V in Figure 18), the Brown-out Reset is immediately activated. When V the trigger level (V out period t The BOD circuit will only detect a drop in V for longer than t Figure ...
Page 41
Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 2 – BORF: Brown-out ...
Page 42
Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value other V interval can be adjusted as shown in Table 21 on page 43. The ...
Page 43
Watchdog Timer Control Register – WDTCR • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega169 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set ...
Page 44
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Note: ...
Page 45
In the same operation, write a logical one to WDCE and WDE. Even though the 2. Within the next four clock cycles, in the same operation, write the WDP bits as 2514H–AVR–05/03 WDE always is set, the WDE must ...
Page 46
Interrupts This section describes the specifics of the interrupt handling as performed in ATmega169. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Interrupt Vectors in Table 22. Reset and Interrupt ...
Page 47
Table 23 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these ...
Page 48
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
Page 49
When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typ- ical and general program setup for the Reset ...
Page 50
Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...
Page 51
I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the ...
Page 52
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Ports as General Digital The ports are bi-directional I/O ports with optional ...
Page 53
Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. Switching Between Input and ...
Page 54
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...
Page 55
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...
Page 56
Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be ...
Page 57
Figure 25. Alternate Port Functions Note: 2514H–AVR–05/03 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 Pxn 0 DIEOExn DIEOVxn 1 SLEEP 0 PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION ...
Page 58
Table 25 summarizes the function of the overriding signals. The pin and port indexes from Figure 25 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table 25. ...
Page 59
MCU Control Register – MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ...
Page 60
Table 28. Overriding Signals for Alternate Functions in PA3..PA0 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 29. Table 29. Port B Pins Alternate Functions The alternate pin configuration is as follows: ...
Page 61
OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this ...
Page 62
SCK/PCINT9 – Port B, Bit 1 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1. When ...
Page 63
Table 31. Overriding Signals for Alternate Functions in PB3..PB0 Alternate Functions of Port C The Port C has an alternate function as the SEG5:12 for the LCD Controller Table 32. Port C Pins Alternate Functions 2514H–AVR–05/03 Signal PB3/MISO/ PB2/MOSI/ Name ...
Page 64
Table 33 and Table 34 relate the alternate functions of Port C to the overriding signals shown in Figure 25 on page 57. Table 33. Overriding Signals for Alternate Functions in PC7..PC4 Table 34. Overriding Signals for Alternate Functions in ...
Page 65
Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 35. Table 35. Port D Pins Alternate Functions The alternate pin configuration is as follows: • SEG15 - SEG20 – Port D, Bit 7:2 ...
Page 66
Table 36 and Table 37 relates the alternate functions of Port D to the overriding signals shown in Figure 25 on page 57. Table 36. Overriding Signals for Alternate Functions PD7..PD4 Table 37. Overriding Signals for Alternate Functions in PD3..PD0 ...
Page 67
Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 38. Table 38. Port E Pins Alternate Functions • PCINT7 – Port E, Bit 7 PCINT7, Pin Change Interrupt Source 7: The PE7 pin ...
Page 68
XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART operates in synchronous ...
Page 69
Table 40. Overriding Signals for Alternate Functions in PE3..PE0 Note: Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in Table 41. If some Port F pins are configured ...
Page 70
TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Regis- ter. When the JTAG interface is enabled, this pin can not ...
Page 71
Table 43. Overriding Signals for Alternate Functions in PF3..PF0 Alternate Functions of Port G The alternate pin configuration is as follows: Table 44. Port G Pins Alternate Functions The alternate pin configuration is as follows: • T0/SEG23 – Port G, ...
Page 72
Table 44 and Table 45 relates the alternate functions of Port G to the overriding signals shown in Figure 25 on page 57. Table 45. Overriding Signals for Alternate Functions in PG4 Table 46. Overriding Signals for Alternate Functions in ...
Page 73
Register Description for I/O-Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input ...
Page 74
Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE ...
Page 75
Port F Input Pins Address – PINF Port G Data Register – PORTG Port G Data Direction Register – DDRG Port G Input Pins Address – PING 2514H–AVR–05/03 Bit PINF7 PINF6 PINF5 Read/Write R/W R/W R/W Initial ...
Page 76
External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT15..0 pins are configured as outputs. This feature provides a ...
Page 77
External Interrupt Mask Register – EIMSK • Bit 7 – PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. ...
Page 78
Bit 0 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set ...
Page 79
Timer/Counter0 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: with PWM • • • • • • • Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 26. For ...
Page 80
Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter ...
Page 81
Depending of the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer ...
Page 82
The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of ...
Page 83
Compare Match Output The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Gener- ator uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next Unit compare match. Also, the COM0A1:0 bits control the OC0A ...
Page 84
Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM0A1:0) bits. The Compare Output mode bits ...
Page 85
OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can ...
Page 86
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM mode, the compare unit allows generation ...
Page 87
Figure 32. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOT- TOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. ...
Page 88
Timer/Counter Timing The Timer/Counter is a synchronous design and the timer clock (clk Diagrams shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 33 contains timing data ...
Page 89
Figure 36 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 36. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f 8-bit Timer/Counter Register Description Timer/Counter Control Register A – TCCR0A • ...
Page 90
Table 49. Waveform Generation Mode Bit Description Note: • Bit 5:4 – COM01:0: Compare Match Output Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides ...
Page 91
Table 52 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode. Table 52. Compare Output Mode, Phase Correct PWM Mode Note: • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits ...
Page 92
Output Compare Register A – OCR0A The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform ...
Page 93
Timer/Counter0 and Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to Timer/Counter1 both Timer/Counter1 and Timer/Counter0. Prescalers Internal Clock Source The Timer/Counter can be clocked directly by the ...
Page 94
However, due to vari- ation of the system clock frequency and duty cycle caused by Oscillator source ...
Page 95
The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: Timer/Counter1 • • • • • • • • • • • Overview Most register and bit ...
Page 96
Figure 39. 16-bit Timer/Counter Block Diagram Note: Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the ...
Page 97
Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin ...
Page 98
Accessing 16-bit The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or Registers write operations. Each 16-bit timer ...
Page 99
Therefore, when both the main code and the interrupt code update the temporary regis- ter, the main code must disable the interrupts during the 16-bit access. The following code examples show how atomic read of the TCNT1 ...
Page 100
The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Note: The assembly code example requires that the ...
Page 101
Timer/Counter Clock The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select Sources (CS12:0) bits located in the Timer/Counter control ...
Page 102
Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 107. The Timer/Counter Overflow Flag (TOV1) is set according to the mode of ...
Page 103
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value ...
Page 104
Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. ...
Page 105
Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However ...
Page 106
Compare Match Output The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener- ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Unit compare match. Secondly the COM1x1:0 bits control the OC1x ...
Page 107
Compare Output Mode and The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM Waveform Generation modes. For all modes, setting the COM1x1 tells the Waveform Generator that no action on the OC1x Register is ...
Page 108
Clear Timer on Compare In Clear Timer on Compare or CTC mode (WGM13 12), the OCR1A or ICR1 Match (CTC) Mode Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to ...
Page 109
Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13 14, or 15) pro- vides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its ...
Page 110
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a ...
Page 111
Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like ...
Page 112
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT- TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle ...
Page 113
Phase and Frequency Correct The phase and frequency correct Pulse Width Modulation, or phase and frequency cor- PWM Mode rect PWM mode (WGM13 provides a high resolution phase and frequency correct PWM waveform generation option. The ...
Page 114
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A ...
Page 115
Timer/Counter Timing The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures. The figures include information Diagrams on when Interrupt Flags are set, and when the OCR1x Register is ...
Page 116
Figure 50. Timer/Counter Timing Diagram, no Prescaling Figure 51 shows the same timing data, but with the prescaler enabled. Figure 51. Timer/Counter Timing Diagram, with Prescaler (f ATmega169V/L 116 clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 ...
Page 117
Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare ...
Page 118
Table 57 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 57. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM Note: • ...
Page 119
Table 58. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
Page 120
Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ...
Page 121
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. Timer/Counter1 – TCNT1H and TCNT1L The ...
Page 122
Input Capture Register 1 – ICR1H and ICR1L The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can ...
Page 123
Timer/Counter1 Interrupt Flag Register – TIFR1 • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to ...
Page 124
Timer/Counter2 Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: with PWM and • Asynchronous • • Operation • • • • Overview A simplified block diagram of the 8-bit Timer/Counter is shown in ...
Page 125
The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Register (OCR2A) is compared with the Timer/Counter ...
Page 126
Depending on the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22 the timer ...
Page 127
The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of ...
Page 128
Compare Match Output The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Gener- ator uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next Unit compare match. Also, the COM2A1:0 bits control the OC2A ...
Page 129
Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM2A1:0) bits. The Compare Output mode bits ...
Page 130
The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A output can be set ...
Page 131
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM mode, the compare unit allows generation ...
Page 132
Figure 58. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT- TOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. ...
Page 133
Timer/Counter Timing The following figures show the Timer/Counter in synchronous mode, and the timer clock Diagrams (clk be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 59 contains timing data ...
Page 134
Figure 61. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f Figure 62 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 62. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f ...
Page 135
Timer/Counter Register Description Timer/Counter Control Register A– TCCR2A • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this ...
Page 136
Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O ...
Page 137
Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 65. Table 65. Clock Select Bit Description Timer/Counter Register – TCNT2 The Timer/Counter Register gives direct ...
Page 138
Asynchronous operation of the Timer/Counter Asynchronous Status Register – ASSR • Bit 4 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external ...
Page 139
Asynchronous Operation of When Timer/Counter2 operates asynchronously, some considerations must be taken. Timer/Counter2 • • • • • • 2514H–AVR–05/03 Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. ...
Page 140
Timer/Counter2 Interrupt Mask Register – TIMSK2 • Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the ...
Page 141
Timer/Counter2 Interrupt Flag Register – TIFR2 • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A ...
Page 142
Timer/Counter Prescaler Figure 63. Prescaler for Timer/Counter2 The clock source for Timer/Counter2 is named clk the main system I/O clock clk chronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 ...
Page 143
Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega169 and peripheral devices or between several AVR devices. The Interface – SPI ATmega169 SPI includes the following features: • • • • • • • ...
Page 144
When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts ...
Page 145
The following code examples show how to initialize the SPI as a Master and how to per- form a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO ...
Page 146
The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. Note: ATmega169V/L 146 (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ...
Page 147
SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the ...
Page 148
Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, ...
Page 149
SPI Status Register – SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If ...
Page 150
Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 66 and Figure 67. Data bits ...
Page 151
USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • • • • • • • • • • • • Overview A simplified block diagram of ...
Page 152
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation logic consists of synchronization logic for ...
Page 153
Figure 69. Clock Generation Logic, Block Diagram Signal description: Internal Clock Generation – Internal clock generation is used for the asynchronous and the synchronous master The Baud Rate Generator modes of operation. The description in this section refers to Figure ...
Page 154
Table 71. Equations for Calculating Baud Rate Register Setting Note: Some examples of UBRR values for some system clock frequencies are found in Table 79 (see page 174). Double Speed Operation The transfer rate can be doubled by setting the ...
Page 155
Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the ...
Page 156
The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt ...
Page 157
The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous opera- tion using polling (no interrupts enabled) and a fixed frame format. The baud rate is given ...
Page 158
Data Transmission – The The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the USART Transmitter TxD pin is overridden by the USART ...
Page 159
Sending Frames with 9 Data If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in Bit UCSRB before the low byte of the character is written to UDR. The following code ...
Page 160
Transmitter Flags and The USART Transmitter has two flags that indicate its state: USART Data Register Interrupts Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts. The Data Register Empty (UDRE) Flag indicates whether the ...
Page 161
Data Reception – The The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the USART Receiver RxD pin is overridden by ...
Page 162
Receiving Frames with 9 Data If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in Bits UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and ...
Page 163
The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as ...
Page 164
Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the ...
Page 165
Asynchronous Clock The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig- Recovery ure 72 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for ...
Page 166
Figure 74 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 74. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the ...
Page 167
Table 72. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) Table 73. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) The recommendations of the maximum receiver baud rate error was ...
Page 168
Multi-processor Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil- tering function of incoming frames received by the USART Receiver. Frames that do not Communication Mode contain address information will be ignored and not put into the ...
Page 169
USART Register Description USART I/O Data Register – UDR The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) ...
Page 170
Bit 5 – UDRE: USART Data Register Empty The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE ...
Page 171
USART Control and Status Register B – UCSRB • Bit 7 – RXCIE: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete interrupt will be generated only if the RXCIE ...
Page 172
USART Control and Status Register C – UCSRC • Bit 6 – UMSEL: USART Mode Select This bit selects between asynchronous and synchronous mode of operation. Table 74. UMSEL Bit Settings • Bit 5:4 – UPM1:0: Parity Mode These bits ...
Page 173
Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character SiZe frame the Receiver and Transmitter use. Table 77. UCSZ Bits Settings • Bit ...
Page 174
Examples of Baud Rate For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 79. Setting UBRR values which yield an actual baud rate differing ...
Page 175
Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
Page 176
Table 81. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
Page 177
Table 82. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
Page 178
Universal Serial The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows Interface – USI significantly higher transfer rates and uses less code space than ...
Page 179
The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the ...
Page 180
The Three-wire mode timing is shown in Figure 77. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown ...
Page 181
The following code demonstrates how to use the USI module as a SPI Master with max- imum speed (fsck = fck/4): SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: The ...
Page 182
Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag is set. Two-wire ...
Page 183
Figure 79. Two-wire Mode, Typical Timing Diagram Referring to the timing diagram (Figure 79.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while 2. In ...
Page 184
Start Condition Detector The start condition detector is shown in Figure 80. The SDA line is delayed (in the range 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled ...
Page 185
Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the Shift Register. USI Status Register – USISR The Status Register contains Interrupt Flags, line Status Flags and the counter ...
Page 186
Note that even when no wire mode is selected (USIWM1.. the external clock input (USCK/SCL) are can still be used by the counter. USI Control Register – USICR The Control Register includes interrupt enable control, wire mode setting, ...
Page 187
Table 83. Relations between USIWM1..0 and the USI Operation Note: 2514H–AVR–05/03 USIWM1 USIWM0 Description 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal Three-wire mode. Uses DO, DI, and USCK pins. The Data ...
Page 188
Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data ...
Page 189
Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...
Page 190
Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of ...
Page 191
Analog Comparator It is possible to select any of the ADC7..0 pins to replace the negative input to the Ana- log Comparator. The ADC multiplexer is used to select this input, and consequently, the Multiplexed Input ADC must be switched ...
Page 192
Analog to Digital Converter Features • • • • • • • • • • • • • • The ATmega169 features a 10-bit successive approximation ADC. The ADC is con- nected to an 8-channel Analog Multiplexer which allows eight ...
Page 193
Figure 82. Analog to Digital Converter Block Schematic Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin ...
Page 194
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If ...
Page 195
ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is ...
Page 196
ADC Conversion Complete, each conversion will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after every conversion. In Free Running mode, a new conversion will be started immediately after the conver- sion completes, while ...
Page 197
Figure 88. ADC Timing Diagram, Free Running Conversion Table 87. ADC Conversion Time Differential Channels When using differential channels, certain aspects of the conversion need to be taken into consideration. Differential conversions are synchronized to the internal clock CK ADC ...
Page 198
Changing Channel or The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem- porary register to which the CPU has random access. This ensures that the channels Reference Selection and reference selection only takes place ...
Page 199
ADC Voltage Reference The reference voltage for the ADC (V Single ended channels that exceed V selected as either AVCC, internal 1.1V reference, or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 1.1V ...
Page 200
Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 89. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is ...