ATMEGA169L-8MI Atmel, ATMEGA169L-8MI Datasheet - Page 197

• Manufacturer Part Number: ATMEGA169L-8MI
• Description: IC MCU AVR 16K LV 8MHZ IND 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169L-8MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA169L-4MI; ATMEGA169L-4MI

Differential Channels
2514H–AVR–05/03
Figure 88. ADC Timing Diagram, Free Running Conversion
Table 87. ADC Conversion Time
When using differential channels, certain aspects of the conversion need to be taken
into consideration.
Differential conversions are synchronized to the internal clock CK
ADC clock. This synchronization is done automatically by the ADC interface in such a
way that the sample-and-hold occurs at a specific phase of CK
ated by the user (i.e., all single conversions, and the first free running conversion) when
CK
clock cycles from the next prescaled clock cycle). A conversion initiated by the user
when CK
nism. In Free Running mode, a new conversion is initiated immediately after the
previous conversion completes, and since CK
started (i.e., all but the first) Free Running conversions will take 14 ADC clock cycles.
If differential channels are used and conversions are started by Auto Triggering, the
ADC must be switched off between conversions. When Auto Triggering is used, the
ADC prescaler is reset before the conversion is started. Since the stage is dependent of
a stable ADC clock prior to the conversion, this conversion will not be valid. By disabling
and then re-enabling the ADC between each conversion (writing ADEN in ADCSRA to
“0” then to “1”), only extended conversions are performed. The result from the extended
conversions will be valid. See “Prescaling and Conversion Timing” on page 195 for tim-
ing details.
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Normal conversions, differential
ADC2
is low will take the same amount of time as a single ended conversion (13 ADC
ADC2
is high will take 14 ADC clock cycles due to the synchronization mecha-
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Conversion
Complete
One Conversion
11
Sample & Hold (Cycles
from Start of Conversion)
12
13
1.5/2.5
14.5
Next Conversion
1
1.5
Sign and MSB of Result
LSB of Result
ADC2
2
2
MUX and REFS
Update
is high at this time, all automatically
3
ATmega169V/L
Sample & Hold
4
ADC2
Conversion Time
ADC2
. A conversion initi-
(Cycles)
equal to half the
13/14
13.5
25
13
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