ATMEGA169L-8MI Atmel, ATMEGA169L-8MI Datasheet - Page 62

• Manufacturer Part Number: ATMEGA169L-8MI
• Description: IC MCU AVR 16K LV 8MHZ IND 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169L-8MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA169L-4MI; ATMEGA169L-4MI

62
ATmega169V/L
• SCK/PCINT9 – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB1 bit.
PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt
source.
• SS/PCINT8 – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured
as an input regardless of the setting of DDB0. As a Slave, the SPI is activated when this
pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is
controlled by DDB0. When the pin is forced to be an input, the pull-up can still be con-
trolled by the PORTB0 bit
PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt
source.
Table 30 and Table 31 relate the alternate functions of Port B to the overriding signals
shown in Figure 25 on page 57. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute
the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE
INPUT.
Table 30. Overriding Signals for Alternate Functions in PB7..PB4
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
PB7/OC2A/
PCINT15
0
0
0
0
OC2A ENABLE
OC2A
–
PCINT15 •
PCIE1
1
PCINT15 INPUT
–
PB6/OC1B/
PCINT14
0
0
0
0
OC1B ENABLE
OC1B
–
PCINT14 • PCIE1
1
PCINT14 INPUT
–
PB5/OC1A/
PCINT13
0
0
0
0
OC1A ENABLE
OC1A
–
PCINT13 • PCIE1
1
PCINT13 INPUT
–
PB4/OC0A/
PCINT12
0
0
0
0
OC0A ENABLE
OC0A
–
PCINT12 •
PCIE1
1
PCINT12 INPUT
–
2514H–AVR–05/03