PIC32MX675F512L-80I/PF Microchip Technology, PIC32MX675F512L-80I/PF Datasheet - Page 63
![IC MCU 32BIT 512KB FLASH 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC32MX675F512L-80I/PF
Manufacturer Part Number
PIC32MX675F512L-80I/PF
Description
IC MCU 32BIT 512KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX675F512L-80I/PF
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP
Controller Family/series
PIC32
Ram Memory Size
64KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC32MX320F032H-40IPT PDF datasheet
- PIC32MX575F256H-80IMR PDF datasheet #2
- PIC32MX575F256H-80IMR PDF datasheet #3
- PIC32MX575F256H-80IMR PDF datasheet #4
- PIC32MX575F256H-80IPT PDF datasheet #5
- Current page: 63 of 240
- Download datasheet (3Mb)
TABLE 4-9:
Legend:
Note
2000 IC1CON
2010
2200 IC2CON
2210
2400 IC3CON
2410
2600 IC4CON
2610
2800 IC5CON
2810
1:
IC1BUF
IC2BUF
IC3BUF
IC4BUF
IC5BUF
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
(1)
(1)
(1)
(1)
(1)
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
INPUT CAPTURE1-INPUT CAPTURE5 REGISTER MAP
31/15
ON
ON
ON
ON
ON
—
—
—
—
—
30/14
FRZ
FRZ
FRZ
FRZ
FRZ
—
—
—
—
—
29/13
SIDL
SIDL
SIDL
SIDL
SIDL
—
—
—
—
—
28/12
—
—
—
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
—
—
—
26/10
—
—
—
—
—
—
—
—
—
—
ICFEDGE
ICFEDGE
ICFEDGE
ICFEDGE
ICFEDGE
25/9
—
—
—
—
—
ICC32
ICC32
ICC32
ICC32
ICC32
24/8
IC1BUF<31:0>
IC2BUF<31:0>
IC3BUF<31:0>
IC4BUF<31:0>
IC5BUF<31:0>
—
—
—
—
—
Bits
ICTMR
ICTMR
ICTMR
ICTMR
ICTMR
23/7
—
—
—
—
—
22/6
—
—
—
—
—
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
21/5
—
—
—
—
—
ICOV
ICOV
ICOV
ICOV
ICOV
20/4
—
—
—
—
—
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
19/3
—
—
—
—
—
18/2
—
—
—
—
—
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
17/1
—
—
—
—
—
16/0
—
—
—
—
—
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
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