PIC32MX675F512L-80I/PF Microchip Technology, PIC32MX675F512L-80I/PF Datasheet - Page 68
![IC MCU 32BIT 512KB FLASH 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC32MX675F512L-80I/PF
Manufacturer Part Number
PIC32MX675F512L-80I/PF
Description
IC MCU 32BIT 512KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX675F512L-80I/PF
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP
Controller Family/series
PIC32
Ram Memory Size
64KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC32MX320F032H-40IPT PDF datasheet
- PIC32MX575F256H-80IMR PDF datasheet #2
- PIC32MX575F256H-80IMR PDF datasheet #3
- PIC32MX575F256H-80IMR PDF datasheet #4
- PIC32MX575F256H-80IPT PDF datasheet #5
- Current page: 68 of 240
- Download datasheet (3Mb)
TABLE 4-13:
Legend:
Note
6000 U1AMODE
6010
6020 U1ATXREG
6030 U1ARXREG
6040 U1ABRG
6200 U1BMODE
6210
6220 U1BTXREG
6230 U1BRXREG
6240 U1BBRG
6400 U2AMODE
6410
6420 U2ATXREG
6430 U2ARXREG
6440 U2ABRG
6600 U2BMODE
6610
1:
U1ASTA
U1BSTA
U2ASTA
U2BSTA
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
UART1A, UART1B, UART2A, UART2B, UART3A, AND UART3B REGISTER MAP
31/15
ON
ON
ON
ON
UTXISEL<1:0>
UTXISEL<1:0>
UTXISEL<1:0>
UTXISEL<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
FRZ
FRZ
FRZ
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXINV
UTXINV
UTXINV
UTXINV
29/13
SIDL
SIDL
SIDL
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
URXEN
URXEN
URXEN
URXEN
28/12
IREN
IREN
IREN
IREN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBRK
UTXBRK
UTXBRK
UTXBRK
RTSMD
RTSMD
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXEN
UTXEN
UTXEN
UTXEN
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBF
UTXBF
UTXBF
UTXBF
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UEN<1:0>
UEN<1:0>
ADM_EN
ADM_EN
ADM_EN
ADM_EN
TRMT
TRMT
TRMT
TRMT
24/8
TX8
RX8
TX8
RX8
TX8
RX8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<15:0>
BRG<15:0>
BRG<15:0>
Bits
WAKE
WAKE
WAKE
WAKE
23/7
URXISEL<1:0>
URXISEL<1:0>
URXISEL<1:0>
URXISEL<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
LPBACK
LPBACK
LPBACK
LPBACK
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
ABAUD
ADDEN
ABAUD
ADDEN
ABAUD
ADDEN
ABAUD
ADDEN
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
RXINV
RXINV
RXINV
RXINV
RIDLE
RIDLE
RIDLE
RIDLE
Transmit Register
Transmit Register
Transmit Register
Receive Register
Receive Register
Receive Register
20/4
—
—
—
—
—
—
—
—
—
—
—
—
—
ADDR<7:0>
ADDR<7:0>
ADDR<7:0>
ADDR<7:0>
BRGH
BRGH
BRGH
BRGH
PERR
PERR
PERR
PERR
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
FERR
FERR
FERR
FERR
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
PDSEL<1:0>
PDSEL<1:0>
PDSEL<1:0>
PDSEL<1:0>
OERR
OERR
OERR
OERR
17/1
—
—
—
—
—
—
—
—
—
—
—
—
—
URXDA
URXDA
URXDA
URXDA
STSEL
STSEL
STSEL
STSEL
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000
0000
0000
0000
0110
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