ST10R167-Q3 STMicroelectronics, ST10R167-Q3 Datasheet - Page 26

IC MCU 16BIT ROMLESS 144-PQFP

ST10R167-Q3

Manufacturer Part Number
ST10R167-Q3
Description
IC MCU 16BIT ROMLESS 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10R167-Q3

Core Processor
ST10
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-QFP
Processor Series
ST10R1x
Core
ST10
Data Bus Width
16 bit
Program Memory Size
32 KB
Data Ram Size
4 KB
Interface Type
CAN/SSC/USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
111
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-2043

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ST10R167
XIV - CAN MODULE
The integrated CAN module handles the com-
pletely autonomous transmission and reception of
CAN frames in accordance with the CAN specifi-
cation V2.0 part B (active) i.e. the on-chip CAN
module can receive and transmit standard frames
with 11-bit identifiers as well as extended frames
with 29-bit identifiers.
The CAN module provides full CAN functionality
on up to 15 message objects. Message object 15
can be configured for basic CAN functionality.
Both modes provide separate masks for accep-
tance filtering, allowing a number of identifiers in
full CAN mode to be accepted and disregarding a
number of identifiers in basic CAN mode.
All message objects can be updated independent
from other objects and are equipped for the maxi-
mum message length of 8 Byte.
The bit timing is derived from the XCLK and is pro-
grammable up to a data rate of 1M Baud. The
CAN module uses two pins to interface to a bus
transceiver.
Table 12 : Watchdog time range for 25MHz CPU clock
26/63
Reload value in WDTREL
FF
00
H
H
2 (WDTIN = ‘0’)
20.48 s
5.24ms
XV - WATCHDOG TIMER
The Watchdog Timer is a fail-safe mechanism
which prevents the microcontroller from malfunc-
tioning for long periods of time. The Watchdog
Timer is always enabled after a reset of the chip
and can only be disabled in the time interval until
the EINIT (end of initialization) instruction has
been executed. Therefore, the chip start-up pro-
cedure is always monitored. The software must
be designed to service the watchdog timer before
it overflows. If, due to hardware or software
related failures, the software fails to do so, the
watchdog timer overflows and generates an inter-
nal hardware reset. It pulls the RSTOUT pin low in
order to allow external hardware components to
be reset.
The Watchdog Timer is 16-bit, clocked with the
system clock divided by 2 or 128. The high Byte of
the watchdog timer register can be set to a
pre-specified reload value (stored in WDTREL).
Each time it is serviced by the application soft-
ware, the high Byte of the watchdog timer is
reloaded. For security, rewrite WDTCON each
time before the watchdog timer is serviced
Prescaler for f
CPU
128 (WDTIN = ‘1’)
1.31ms
336ms

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