ST10R167-Q3 STMicroelectronics, ST10R167-Q3 Datasheet - Page 46

• Manufacturer Part Number: ST10R167-Q3
• Description: IC MCU 16BIT ROMLESS 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R167-Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10R1x
• Core: ST10
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 4 KB
• Interface Type: CAN/SSC/USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-2043

ST10R167
XX - ELECTRICAL CHARACTERISTICS (continued)
Table 18 : Multiplexed bus characteristics (continued)
46/63
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
19
44
45
11
12
13
14
15
16
17
18
22
23
25
27
38
39
40
42
43
46
47
Symbol
1
1
1
1
1
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
CC
SR
CC
CC
CC
CC
CC
SR
SR
Address float after RD, WR
(with RW-delay)
Address float after RD, WR (no
RW-delay)
RD, WR low time (with RW-delay)
RD, WR low time (no RW-delay)
RD to valid data in (with
RW-delay)
RD to valid data in (no RW-delay)
ALE low to valid data in
Address/Unlatched CS to valid
data in
Data hold after RD rising edge
Data float after RD
Data valid to WR
Data hold after WR
ALE rising edge after RD, WR
Address/Unlatched CS hold after
RD, WR
ALE falling edge to Latched CS
Latched CS low to valid data in
Latched CS hold after RD, WR
ALE fall. edge to RdCS, WrCS
(with RW delay)
ALE fall. edge to RdCS, WrCS
(no RW delay)
Address float after RdCS, WrCS
(with RW delay)
Address float after RdCS, WrCS
(no RW delay)
RdCS to Valid Data In (with RW
delay)
RdCS to Valid Data In (no RW
delay)
Parameter
30 + t
50 + t
20 + t
26 + t
26 + t
26 + t
46 + t
16 + t
-4 + t
-4 - t
Min.
–
–
–
–
–
–
0
–
–
–
–
–
–
Max. CPU Clock
A
A
C
C
C
F
F
F
F
A
= 25MHz
50 + 2t
40 + t
40 + t
20 + t
40 + t
16 + t
36 + t
26 + t
10 - t
Max.
26
20
C
6
–
–
–
–
–
–
–
–
–
–
0
A
A
+ 2t
+ t
A
C
C
C
C
F
+ t
C
C
A
2TCL - 10 + t
3TCL - 10 + t
2TCL - 20 + t
2TCL - 14 + t
2TCL - 14 + t
2TCL - 14 + t
3TCL - 14 + t
TCL - 4 + t
-4 + t
-4 - t
Min.
1/2TCL = 1 to 25MHz
Variable CPU Clock
–
–
–
–
–
–
0
–
–
–
–
–
–
A
A
A
C
C
C
F
F
F
F
2TCL - 24 + t
3TCL - 24 + t
2TCL - 14 + t
2TCL - 20+ t
3TCL - 20+ t
3TCL - 20
4TCL - 30
3TCL - 20
+ 2t
+ t
+ t
TCL + 6
10 - t
Max.
C
TCL
A
A
6
–
–
–
–
–
–
–
–
–
–
0
+ 2t
+ t
+ t
A
C
C
A
C
C
F
C
C
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns