ST10R167-Q3 STMicroelectronics, ST10R167-Q3 Datasheet - Page 44

• Manufacturer Part Number: ST10R167-Q3
• Description: IC MCU 16BIT ROMLESS 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R167-Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10R1x
• Core: ST10
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 4 KB
• Interface Type: CAN/SSC/USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-2043

ST10R167
XX - ELECTRICAL CHARACTERISTICS (continued)
The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes F
locked on F
the maximum when it is refered to one TCL
period. It decreases according to the formula and
to the Figure 12 given below. For N periods of
TCL the minimum value is computed using the
corresponding deviation D
Figure 12 : Approximated maximum PLL jitter
XX.4.7 - Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and represent the
special characteristics of the programmed memory cycle. The following table describes how these
variables are to be computed.
44/63
Symbol
t
t
t
A
C
F
Max.jitter [%]
±4
±3
±2
±1
TCL MIN
XTAL
ALE Extension
Memory Cycle Time wait states
Memory Tristate Time
D N
2
. The relative deviation of TCL is
=
=
TCL NOM
4
4 N 15 %
–
N
:
8
1
–
CPU
-------------
100
D
N
Description
to keep it
16
where N = number of consecutive TCL periods
and 1
(N = 3):
D
3TCL
3TCL
This is especially important for bus cycles using
wait states and for the operation of timers, serial
interfaces, etc. For all slower operations and
longer periods (e.g. pulse train generation or
measurement,
deviation caused by the PLL jitter is negligible.
3
This approximated formula is valid for
1
min
min
N
N
40 and 10MHz
= 4 - 3/15 = 3.8%
= 3TCL
= 3TCL
= (57.72ns at f
40. So for a duration of 3 TCL periods
lower
NOM
NOM
x (1 - 3.8/100)
x 0.962
Baud
CPU
2TCL * (15 - <MCTC>)
f
2TCL * (1 - <MTTC>)
CPU
32
TCL * <ALECTL>
= 25MHz)
rates,
Values
25MHz.
N
etc.)
the