MC9S08GT16ACFDE Freescale Semiconductor, MC9S08GT16ACFDE Datasheet - Page 195
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MC9S08GT16ACFDE
Manufacturer Part Number
MC9S08GT16ACFDE
Description
IC MCU 16K FLASH 2K RAM 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08GT8ACFBER.pdf
(300 pages)
Specifications of MC9S08GT16ACFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
39
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
QFN EP
Processor Series
S08GT
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
39
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Minimum Operating Temperature
- 40 C
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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12.4.3
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
Freescale Semiconductor
SPPR[2:0]
MODFEN
BIDIROE
SPISWAI
SPR[2:0]
Reset
SPC0
Field
Field
6:4
2:0
4
3
1
0
W
R
SPI Baud Rate Register (SPIBR)
Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer
to
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
SPI Stop in Wait Mode
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI
uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the
MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the
output driver for the single bidirectional SPI I/O pin.
0 SPI uses separate pins for data input and data output
1 SPI configured for single-wire bidirectional operation
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in
drives the input of the SPI baud rate divider (see
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table
divider is the SPI bit rate clock for master mode.
0
0
7
Table 12-2
12-6. The input to this divider comes from the SPI baud rate prescaler (see
= Unimplemented or Reserved
Table
SPPR2
for more details).
0
6
12-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
Table 12-4. SPIBR Register Field Descriptions
Table 12-3. SPIC2 Register Field Descriptions
Figure 12-8. SPI Baud Rate Register (SPIBR)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
SPPR1
0
5
SPPR0
0
4
Figure
Description
Description
12-5).
3
0
0
SPR2
0
2
Serial Peripheral Interface (S08SPIV3)
Figure
12-5). The output of this
SPR1
0
1
SPR0
0
0
195
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