MC908JL16CSPE Freescale Semiconductor, MC908JL16CSPE Datasheet - Page 97

IC MCU 16K FLASH 8MHZ 32-SDIP

MC908JL16CSPE

Manufacturer Part Number
MC908JL16CSPE
Description
IC MCU 16K FLASH 8MHZ 32-SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908JL16CSPE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Controller Family/series
HC08
No. Of I/o's
26
Ram Memory Size
512Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Processor Series
HC08JL
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908JL16E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
For Use With
DEMO908JL16E - BOARD DEMO FOR MC908JL16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
7.5.1 Wait Mode
The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
Refer to
7.5.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect SCI register states. SCI module operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
Refer to
7.6 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
7.7 I/O Signals
The two SCI I/O pins are:
7.7.1 TxD (Transmit Data)
The PTD6/TxD/SCL pin is the serial data output from the SCI transmitter.
7.7.2 RxD (Receive Data)
The PTD7/RxD/SDA pin is the serial data input to the SCI receiver.
Freescale Semiconductor
PTD6/TxD/SCL — Transmit data
PTD7/RxD/SDA — Receive data
4.6 Low-Power Modes
4.6 Low-Power Modes
in for information on exiting wait mode.
for information on exiting stop mode.
MC68HC908JL16 Data Sheet, Rev. 1.1
Low-Power Modes
97

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