C8051F705-GM Silicon Laboratories Inc, C8051F705-GM Datasheet - Page 186

• Manufacturer Part Number: C8051F705-GM
• Description: IC 8051 MCU 15K FLASH 48-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F70xr

Specifications of C8051F705-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 15KB (15K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 32 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: C8051F7x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F700DK
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 1.9 V, 3.6 V
• Supply Voltage (min): 1.7 V, 1.8 V
• Width: 7 mm
• For Use With: 336-1635 - DEV KIT FOR C8051F700
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1612-5

C8051F70x/71x
186
The crossbar peripherals are assigned in priority order from top to bottom, according to this
diagram.
enabled, the Crossbar should be manually configured to skip the corresponding port pins.
* NSS is only pinned out when the SPI is in 4-wire mode.
Pin Number
SYSCLK
Function
Pin Skip
These boxes represent Port pins which can potentially be assigned to a peripheral.
Special Function Signals are not assigned by the crossbar. When these signals are
Pins can be “skipped” by setting the corresponding bit in PnSKIP to 1.
Settings
Special
Signals
CP0A
CEX0
CEX1
CEX2
MISO
MOSI
NSS*
SCK
SDA
RX0
SCL
CP0
Port
TX0
ECI
T0
T1
Figure 28.4. Crossbar Priority Decoder—Possible Pin Assignments
0 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
P0SKIP
P0
0 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Rev. 1.0
P1SKIP
P1
0 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
P2SKIP
P2