MC56F8013VFAE Freescale Semiconductor, MC56F8013VFAE Datasheet
MC56F8013VFAE
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MC56F8013VFAE Summary of contents
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Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8013 Rev. 12 05/2008 freescale.com ...
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... Table 10-7. EI3.3 EI2.5 56F8013/56F8011 Data Sheet, Rev. 12 11-1. 1.4.1, corrected bit selects in Timer Table 10-9. 10-1, corrected Table 8-1, error in Port C Table 10-9 that referred to Table 10-4; moved input current high/low 10-5; reorganized Table 10-19; clarified title Freescale Semiconductor 2-3; ...
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... Updated temperature information in • Fixed miscellaneous errors. Please see http://www.freescale.com for the most current data sheet revision. Freescale Semiconductor Description of Change 10-4, added an entry for flash data retention with less than 100 program/erase 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. ...
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... SSA 2 Digital Reg Analog Reg Low-Voltage 16-Bit Supervisor 56800E Core Data ALU Bit -> 36-Bit MAC Manipulation Three 16-bit Input Registers Unit Four 36-bit Accumulators R/W Control System Bus Control System Integration Clock R S Module Generator* C *Includes On-Chip Relaxation Oscillator Freescale Semiconductor ...
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... Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.8. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Part 7: Security Features . . . . . . . . . . . . . . 84 7.1. Operation with Security Enabled . . . . . . . . 84 7.2. Flash Access Lock and Unlock Mechanisms 85 7.3. Product Analysis . . . . . . . . . . . . . . . . . . . . . 86 Freescale Semiconductor Part 8: General Purpose Input/Output (GPIO 8.1. Introduction 8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 86 8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . . 88 Part 9: Joint Test Action Group (JTAG ...
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... Program Flash (56F8013 device) 12KB of Program Flash (56F8011 device) — 4KB of Unified Data/Program RAM (56F8013 device) 2KB of Unified Data/Program RAM (56F8011 device) • EEPROM emulation capability using Flash 6 Table 1-1 Device Differences 56F8013 16KB 4KB 56F8013/56F8011 Data Sheet, Rev. 12 56F8011 12KB 2KB Freescale Semiconductor ...
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... Programmable Length Transactions ( bits) • One Inter-Integrated Circuit (I — Operates up to 400kbps — Supports both master and slave operation • Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources Freescale Semiconductor 2 C) port 56F8013/56F8011 Data Sheet, Rev. 12 56F8013/56F8011 Features 7 ...
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... Program Flash page erase size is 512 Bytes (256 Words). A full set of programmable peripherals—PWM, ADCs, SCI, SPI, I applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs). 8 56F8013/56F8011 Data Sheet, Rev Quad Timer—supports various Freescale Semiconductor ...
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... GPIOB2 input can be used to drive PWM 0 and 1 — GPIOB3 input can be used to drive PWM 2 and 3 — GPIOB4 input can be used to drive PWM 4 and 5 • Quad Timer output: — Timer0 output can be used to drive PWM 0 and 1 Freescale Semiconductor Figure 1-1, Figure Figure 1-2 Figure 1-3 details how the device’ ...
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... Unit Decoder (AGU) Interrupt M01 Unit N3 Looping Unit Data Y0 Arithmetic X0 Logic Unit (ALU) MAC and ALU Multi-Bit Shifter 56F8013/56F8011 Data Sheet, Rev. 12 ALU1 ALU2 Program R3 Memory XAB1 XAB2 PAB Data / Program PDB RAM CDBW CDBR XDB2 A0 B0 IPBUS C0 Interface D0 Freescale Semiconductor ...
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... CLKGEN (ROSC / PLL / CLKIN) 8 GPIOAn 8 GPIOBn 6 GPIOCn 4 GPIODn Freescale Semiconductor To/From IPBus Bridge GPIO A GPIO B GPIO C GPIO D IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8013/56F8011 Data Sheet, Rev. 12 Multiple Frequency PWM Interrupt Controller Low-Voltage Interrupt POR & LVI System POR ...
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... MISO, MOSI 2 to PWM 3 ANA0 ANA2 REFH REFL ANB2 V 2 ANB0 56F8013/56F8011 Data Sheet, Rev. 12 PWM0 - 3 GPIOA0 - 3 PWM4, 5 Fault1, 2 T2, 3 GPIOA4 - 5 Fault0 GPIOA6 Fault3 T1 GPIOB5 T0 CLKO GPIOB4 GPIOB6 - 7 GPIOB0 - 1 T2, 3 GPIOB2 - 3 ANA0 ANA2 GPIOC0 ANB2 , V REFH REFL GPIOC2, 6 ANB0 GPIOC4 Freescale Semiconductor ...
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... Product Documentation The documents listed in Table 1-2 or 56F8011. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.com Table 1-2 56F8013/56F8011 Chip Documentation Topic DSP56800E Detailed description of the 56800E family architecture, Reference Manual ...
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... Pins in this section can function as Timer Pins can function as PWM and GPIO. 4. Pins in this section can function Table 2-2, each table row describes the signal or Functional Group ) DDA ) SSA and GPIO and GPIO. 56F8013/56F8011 Data Sheet, Rev. 12 Number of Pins Freescale Semiconductor ...
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... GPIOB4, T0, CLKO 20 GPIOA5 GPIOA5, PWM5, FAULT2 GPIOB0 GPIOB0, SCLK, SCL 22 GPIOA4 GPIOA4, PWM4, FAULT1 GPIOA2 GPIOA2, PWM2 24 GPIOA3 GPIOA3, PWM3 Freescale Semiconductor Table 2-2 56F8013/56F8011 Pins Peripherals: GPIO I2C SCI SPI ADC B6 SDA RXD B1 SDA SS B7 SCL TXD B5 C4 ANB0 C5 ANB1 ...
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... GPIOA1 GPIOA1, PWM1 29 GPIOA0 GPIOA0, PWM0 30 TDI TDI, GPIOD0 31 TMS TMS, GPIOD3 32 TDO TDO, GPIOD1 16 Peripherals: GPIO I2C SCI SPI ADC 56F8013/56F8011 Data Sheet, Rev. 12 Quad Power & PWM JTAG Timer Ground V CAP PWM1 PWM0 TDI TMS TDO Freescale Semiconductor Misc. ...
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... C Port or GPIOB7 (TXD, SCL) GPIO RESET RESET (GPIOA7) GPIOB4 (T0, CLKO) Timer Port or GPIO GPIOB5 (T1, FAULT3) TCK (GPIOD2) TMS (GPIOD3) JTAG/ EOnCE Port TDI (GPIOD0) or GPIO TDO (GPIOD1) Figure 2-1 56F8013/56F8011 Signals Identified by Functional Group Freescale Semiconductor DDA 1 V SSA 1 56F8013 / 56F8011 1 V ...
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... Clock Input — This pin serves as an optional external clock input. After reset, the default state is GPIOB6. The alternative peripheral functionality is controlled via the SIM (See CLKMODE bit of the OCCS Oscillator Control Register. 56F8013/56F8011 Data Sheet, Rev. 12 Signal Description Section 10.2. serial data line. Section 6.3.8) and the Freescale Semiconductor ...
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... Input/ Output (T0) Input/ Output (CLKO) Output Return to Table 2-2 Freescale Semiconductor State During Reset Input with Port B GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled Transmit Data — SCI transmit data output or transmit / receive in single wire operation. ...
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... Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDI. 56F8013/56F8011 Data Sheet, Rev. 12 Signal Description Section 6.3.8. through a 2.2K resistor if this pin DD Freescale Semiconductor ...
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... Output 4. This signal is also brought out on the GPIOB6 pin. Return to Table 2-2 Freescale Semiconductor State During Reset Output Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. Port D GPIO — ...
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... Port A GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled PWM0 — This is one of the six PWM output pins. After reset, the default state is GPIOA0. 56F8013/56F8011 Data Sheet, Rev. 12 Signal Description Section 6.3.8. Section 6.3.8. Freescale Semiconductor ...
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... Input 7 Input/ (T2 ) Output 7. This signal is also brought out on the GPIOB2 pin. Return to Table 2-2 Freescale Semiconductor State During Reset Input with Port A GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled PWM1 — This is one of the six PWM output pins. ...
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... After reset, the default state is ANA0. Analog ANA1 — Analog input to ADC A, channel 1 Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is ANA1. 56F8013/56F8011 Data Sheet, Rev. 12 Signal Description Section 6.3.8. Freescale Semiconductor ...
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... Input (V ) Input REFL Input/ (GPIOC6) Output Return to Table 2-2 Freescale Semiconductor State During Reset Analog ANA2 — Analog input to ADC A, channel 2 Input V — Analog reference voltage high REFH Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ...
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... The 2X system clock source output from the OCCS can be described by one of the following equations: 2X system frequency = oscillator frequency 2X system frequency = (oscillator frequency (postscaler) where: postscaler = 16 PLL output divider The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle in the system clock output. 26 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... External Clock Source The recommended method of connecting an external clock is illustrated in source is connected to GPIOB6 / RXD / SDA / CLKIN. Figure 3-1 Connecting an External Clock Signal using GPIOB6 / RXD / SDA / CLKIN Freescale Semiconductor 56F8013/56F8011 GPIOB6 / RXD / SDA / CLKIN External Clock 56F8013/56F8011 Data Sheet, Rev. 12 ...
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... Bus Interface and Control PRECS MSTR_OSC Postscaler ÷ 3 (÷ 16, 32) ÷ 2 Postscaler (÷ 16, 32) LCK Loss of Loss of Reference Clock Interrupt Reference Clock Detector 56F8013/56F8011 Data Sheet, Rev. 12 Bus Interface SYS_CLK_x2 source to the SIM (64MHz max) ZSRC PLLCOD HS PERF CLK (96MHz max) Freescale Semiconductor ...
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... By default, VBA = 0, and the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. Freescale Semiconductor Table Table 4-1 ...
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... P:$36 SPI Transmitter Empty P:$38 SCI Transmitter Empty P:$3A SCI Transmitter Idle P:$3C SCI Reserved P:$3E SCI Receiver Error P:$40 SCI Receiver Full Reserved P:$ P:$48 Timer Channel 0 P:$4A Timer Channel 1 (Continues next page) 56F8013/56F8011 Data Sheet, Rev Interrupt Function 2 Freescale Semiconductor ...
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... P: $00 7FFF P: $00 2000 P: $00 1FFF P: $00 0000 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure Freescale Semiconductor Vector Base Address + P:$4C Timer Channel 2 P:$4E Timer Channel 3 P:$50 ADCA Conversion Complete ...
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... On-Chip RAM 2KB RESERVED Internal Program Flash 12KB Cop Reset Address = $00 0802 Boot Location = $00 0800 RESERVED 4-1. Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 locations allocated RESERVED RESERVED RESERVED 2 On-Chip Data RAM 4KB 56F8013/56F8011 Data Sheet, Rev Freescale Semiconductor ...
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... All addresses are 16-bit Word addresses. 2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-1. Program Reserved RAM Reserved Flash Freescale Semiconductor Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 locations allocated RESERVED 2 On-Chip Data RAM ...
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... Breakpoint Unit Address Register 1 Breakpoint Unit Address Register 2 Breakpoint Unit Address Register 2 Breakpoint Unit Mask Register 2 Breakpoint Unit Mask Register 2 Reserved EOnCE Breakpoint Unit Counter Reserved Reserved Reserved External Signal Control Register Reserved 56F8013/56F8011 Data Sheet, Rev. 12 Register Name Freescale Semiconductor ...
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... Power Supervisor FM Table 4-9 Quad Timer Registers Address Map Register Acronym TMR0_COMP1 TMR0_COMP2 TMR0_CAPT TMR0_LOAD TMR0_HOLD TMR0_CNTR TMR0_CTRL TMR0_SCTRL TMR0_CMPLD1 Freescale Semiconductor Prefix Base Address TMRn X:$00 F000 PWM X:$00 F040 ITCN X:$00 F060 ADC X:$00 F080 SCI X:$00 F0B0 SPI ...
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... Comparator Status and Control Register Reserved $30 Compare Register 1 $31 Compare Register 2 $32 Capture Register $33 Load Register $34 Hold Register $35 Counter Register $36 Control Register $37 Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 $3A Comparator Status and Control Register 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... PWM_SCTRL Table 4-11 Interrupt Control Registers Address Map Register Acronym ITCN_IPR0 ITCN_IPR1 ITCN_IPR2 ITCN_IPR3 ITCN_IPR4 ITCN_VBA ITCN_FIM0 ITCN_FIVAL0 ITCN_FIVAH0 ITCN_FIM1 Freescale Semiconductor (PWM_BASE = $00 F040) Address Offset Register Description $0 Control Register $1 Fault Control Register $2 Fault Status Acknowledge Register $3 Output Control Register $4 Counter Register ...
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... Result Register 7 $11 Low Limit Register 0 $12 Low Limit Register 1 $13 Low Limit Register 2 $14 Low Limit Register 3 $15 Low Limit Register 4 $16 Low Limit Register 5 $17 Low Limit Register 6 $18 Low Limit Register 7 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... SCI_RATE SCI_CTRL1 SCI_CTRL2 SCI_STAT SCI_DATA Table 4-14 Serial Peripheral Interface Registers Address Map Register Acronym SPI_SCTRL SPI_DSCTRL SPI_DRCV SPI_DXMIT Freescale Semiconductor (ADC_BASE = $00 F080) Address Offset Register Description $19 High Limit Register 0 $1A High Limit Register 1 $1B High Limit Register 2 $1C High Limit Register 3 ...
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... Data I/O Register $5 Noise Filter Register (COP_BASE = $00 F0E0) Address Offset Register Description $0 Control Register $1 Time-Out Register $2 Counter Register (OCCS_BASE = $00 F0F0) Address Offset Register Description $0 Control Register $1 Divide-By Register $2 Status Register Reserved $4 Shutdown Register $5 Oscillator Control Register 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... Table 4-19 GPIOB Registers Address Map Register Acronym GPIOB_PUPEN GPIOB_DATA GPIOB_DDIR GPIOB_PEREN GPIOB_IASSRT GPIOB_IEN GPIOB_IEPOL GPIOB_IPEND GPIOB_IEDGE GPIOB_PPOUTM GPIOB_RDATA GPIOB_DRIVE Freescale Semiconductor (GPIOA_BASE = $00 F100) Address Offset Register Description $0 Pull-up Enable Register $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register ...
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... Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register $5 Interrupt Enable Register $6 Interrupt Edge Polarity Register $7 Interrupt Pending Register $8 Interrupt Edge-Sensitive Register $9 Push-Pull Output Mode Control Register $A Raw Data Register $B Drive Strength Control Register 56F8013/56F8011 Data Sheet, Rev. 12 Register Description Freescale Semiconductor ...
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... Table 4-23 Power Supervisor Registers Address Map Register Acronym PS_CTRL PS_STAT Table 4-24 Flash Module Registers Address Map Register Acronym FM_CLKDIV FM_CNFG FM_SECHI FM_SECLO FM_PROT FM_USTAT Freescale Semiconductor (SIM_BASE = $00 F140) Address Offset Register Description $0 Control Register $1 Reset Status Register $2 Software Control Register 0 $3 Software Control Register 1 ...
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... IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to 44 (FM_BASE = $00 F400) Address Offset Register Description $14 Command Register $15 Reserved $16 Reserved $17 Reserved $18 Data Buffer Register $19 Reserved $1A Reserved $1B Optional Data 1 Register Reserved $1D Test Array Signature Register 4-2, Interrupt Vector Table Contents. 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... Wait or Stop mode. Freescale Semiconductor 56F8013/56F8011 Data Sheet, Rev. 12 Functional Description 45 ...
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... The core then fetches the instruction from the indicated vector adddress and not a JSR, the core starts its Fast Interrupt handling. 46 SR[8] Exceptions Permitted 0 Priorities Priorities Priorities Priority 3 56F8013/56F8011 Data Sheet, Rev. 12 Exceptions Masked None Priority 0 Priorities 0, 1 Priorities Fast Interrupt Freescale Semiconductor ...
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... Block Diagram Priority Level 2 -> 4 INT0 Decode Priority Level 2 -> 4 INT45 Decode Figure 5-1 Interrupt Controller Block Diagram Freescale Semiconductor any0 Level 0 46 -> Priority Encoder any3 Level 3 46 -> Priority Encoder 56F8013/56F8011 Data Sheet, Rev. 12 Block Diagram INT VAB CONTROL IPIC ...
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... Fast Interrupt 1 Vector Address High Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 Reserved Interrupt Control Register Reserved 56F8013/56F8011 Data Sheet, Rev. 12 Section Location 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9 5.5.10 5.5.11 5.5.12 5.5.13 5.5.14 5.5.15 5.5.16 Freescale Semiconductor ...
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... ICTRL W Reserved = Reserved Figure 5-2 ITCN Register Map Summary 5.5.1 Interrupt Priority Register 0 (IPR0) Base + $ Read 0 LVI IPL Write RESET Figure 5-3 Interrupt Priority Register 0 (IPR0) Freescale Semiconductor RX_REG IPL TX_REG IPL 0 0 GPIOC IPL GPIOD IPL FM_CBE IPL 0 0 SCI_RERR ...
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... IRQ is priority level 2 • IRQ is priority level 3 5.5.1.6 EOnCE Breakpoint Unit Interrupt Priority Level (BKPT_U IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. 50 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor GPIOD IPL FM_CBE IPL ...
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... FM Error Interrupt Priority Level (FM_ERR IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 52 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.5.3.3 Reserved—Bits 11–10 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor SCI_TIDL IPL SCI_XMIT IPL SPI_XMIT IPL SPI_RCV IPL ...
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... Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 54 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor TMR_2 IPL TMR_1 IPL TMR_0 IPL ...
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... Interrupt Priority Register 4 (IPR4) Base + $ Read Write RESET Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.5.5.1 Reserved—Bits 15–8 This bit field is reserved or not implemented read as 0 and cannot be modified by writing PWM_F IPL 56F8013/56F8011 Data Sheet, Rev ADC_ZC_LE ADCB_CC PWM_RL IPL IPL IPL Freescale Semiconductor ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor 56F8013/56F8011 Data Sheet, Rev. 12 Register Descriptions 57 ...
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... Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to the vector table VECTOR_BASE_ADDRESS 56F8013/56F8011 Data Sheet, Rev FAST INTERRUPT Freescale Semiconductor ...
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... These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having jump table first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast Freescale Semiconductor 12 11 ...
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... Fast Interrupt 1 defined in the FIM1 register. 5.5.13 IRQ Pending Register 0 (IRQP0) Base + $ Read Write RESET Figure 5-15 IRQ Pending Register 0 (IRQP0 FAST INTERRUPT 1 VECTOR ADDRESS LOW PENDING[16: 56F8013/56F8011 Data Sheet, Rev FAST INTERRUPT 1 VECTOR ADDRESS HIGH Freescale Semiconductor ...
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... Figure 5-17 IRQ Pending Register 2 (IRQP2) 5.5.15.1 IRQ Pending (PENDING)—Bits 45–33 This register combines with IRQP0 and IRQP1 to represent the pending IRQs for interrupt vector numbers 2 through 45. • IRQ pending for this vector number • IRQ pending for this vector number Freescale Semiconductor PENDING[32:17] 1 ...
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... Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated when the 56800E core jumps to a new interrupt service routine VAB Current Interrupt Required Nested Priority Level Exception Priority No interrupt or SWILP Priorities Priority 0 Priority 1 Priority 56F8013/56F8011 Data Sheet, Rev INT_ DIS Priorities Priorities 2, 3 Priority 3 Freescale Semiconductor ...
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... The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET is released. The general timing is shown in RES CLK VAB PAB Freescale Semiconductor Table 5-4 Reset Summary Priority Source RST Figure 5-19. ...
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... Stop/Wait control • System status registers • Registers for software access to the JTAG ID of the chip • Test registers • Power control • I/O pad multiplexing These are discussed in more detail in the sections that follow. 64 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... Timer channel Stop mode clocking controls • SCI Stop mode clocking control to support LIN Sleep mode stop recovery • Short addressing location control • Registers for containing the JTAG ID of the chip • Controls output to CLKO pin Freescale Semiconductor 56F8013/56F8011 Data Sheet, Rev. 12 Features 65 ...
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... GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register 56F8013/56F8011 Data Sheet, Rev. 12 Section Location 6.3.1 6.3.2 6.3.3 6.3.3 6.3.3 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.10 Freescale Semiconductor ...
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... TC1_ Write RESET Figure 6-2 SIM Control Register (SIM_CTRL) 6.3.1.1 Timer Channel 3 Stop Disable (TC3_SD)—Bit 15 This bit enables the operation of the Timer Channel 3 peripheral clock in Stop mode. • Timer Channel 3 disabled in Stop mode Freescale Semiconductor TC1_ TC0_ SCI_ TC3_ SD SD ...
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... OnCE Enable (ONCEEBL)—Bit 5 • OnCE clock to 56800E core enabled when core TAP is enabled • OnCE clock to 56800E core is always enabled 6.3.1.10 Software Reset (SWRST)—Bit 4 Writing 1 to this field will cause the part to reset. 68 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... When set, this bit indicates that the previous system reset occurred as a result of a software reset (written 1 to SWRST bit in the SIM_CTRL register). It will not be set if a COP, external, or POR reset also occurred. 6.3.2.3 COP Reset (COPR)—Bit 4 When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly Freescale Semiconductor ...
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... Most Significant Half of JTAG ID (SIM_MSHID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F2. Base + $ Read Write RESET Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID Software Control Data 56F8013/56F8011 Data Sheet, Rev Freescale Semiconductor ...
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... Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset Standby mode can be used when device operates below 200KHz with PLL shut down. 6.3.7 CLKO Select Register (SIM_CLKOUT) The CLKO select register can be used to multiplex out selected clocks generated inside the clock Freescale Semiconductor ...
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... CLKOUT output is enabled and will output the signal indicated by CLKOSEL • CLKOUT is 0 6.3.7.7 Clockout Select (CLKOSEL)—Bits 4–0 Selects clock to be muxed out on the CLKO pin. • 00000 = Reserved for factory test—Continuous system clock PWM3 PWM2 PWM1 PWM0 56F8013/56F8011 Data Sheet, Rev CLK CLKOSEL DIS Freescale Semiconductor ...
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... I/O. SIM_GPS simply decides which peripheral will be routed to the I/O when PEREN = 1. Quad Timer Controlled SCI Controlled Figure 6-9 Overall Control of Pads Using SIM_GPS Control Base + $ Read 0 TCR PCR Write RESET Figure 6-10 GPIO Peripheral Select Register (SIM_GPS) Freescale Semiconductor GPIOB_PEREN Register GPIO Controlled 0 1 SIM_GPS Register CFG_ CFG_ CFG_ CFG_ ...
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... Configure GPIOB6 (CFG_B6)—Bit 10 This bit selects the alternate function for GPIOB6. 74 module’s clock is disabled. See PWM when Using PWM Reload Pulse Quad Timer Clock Speed 56F8013/56F8011 Data Sheet, Rev. 12 Section 6.3.9. Section Table 6-2. Section 6.3.9. Section 6.3.1.7), Table 6- Freescale Semiconductor ...
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... This bit selects the alternate function for GPIOB0. • SCLK — SPI Serial Clock (default) • SCL — I2C Serial Clock 6.3.8.12 Configure GPIOA5[1:0] (CFG_A5)—Bits 3–2 These bits select the alternate function for GPIOA5. Freescale Semiconductor 56F8013/56F8011 Data Sheet, Rev. 12 Register Descriptions 75 ...
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... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.3.9.3 Analog-to-Digital Converter IPBus Clock Enable (ADC)—Bit 13 • The clock is not provided to the ADC module (the ADC module is disabled) • Clocks to the ADC module are enabled 76 NOTE 56F8013/56F8011 Data Sheet, Rev TMR SCI SPI Freescale Semiconductor 0 PWM 0 ...
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... The I/O short address mode allows the instruction to specify the lower six bits of address; the upper address bits are not directly controllable. This register set allows limited control of the full address, as shown in Figure 6-12. Freescale Semiconductor 56F8013/56F8011 Data Sheet, Rev. 12 Register Descriptions 77 ...
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... Input/Output Short Address Location (ISAL[23:22])—Bits 1–0 This field represents the upper two address bits of the “hard coded” I/O short address. 78 “ Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction 56F8013/56F8011 Data Sheet, Rev. 12 Instruction Portion ISAL[23:22 Freescale Semiconductor 0 1 ...
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... Timer channels and PWM but require the PLL and selected. Refer to the 56F801X Peripheral User Manual for further details. 6.5 Power-Down Modes The 56F8013/56F8011 operates in one of five Power-Down modes, as shown in Table 6-3 Clock Operation in Power-Down Modes Mode Core Clocks Run Core and memory clocks disabled Freescale Semiconductor ISAL[21: ...
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... The user configures the OCCS and SIM to enter Standby mode as shown in the previous description, followed by powering down the oscillator (ROPD). The only possible recoveries from this mode are: 1. External Reset 2. Power-On Reset 56F8013/56F8011 Data Sheet, Rev. 12 Description Table 6-3. Run, Wait, and Stop Freescale Semiconductor ...
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... Relaxation Oscillator Clock as their time base since other system clocks are inactive during this phase of reset. 1. The Quad Timer and PWM modules can be operated at three times the IPBus clock frequency. Freescale Semiconductor Figure 6-15. The two asynchronous sources are the ...
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... Resets may be asserted asynchronously, but they are always released internally on a rising edge of the system clock. 82 EXTENDED_POR CLKGEN_RST Delay 32 MSTR_OSC Clocks pulse shaper Delay 32 sys clocks pulse shaper 56F8013/56F8011 Data Sheet, Rev. 12 JTAG Memory Subsystem OCCS PERIP_RST Peripherals 56800E Delay 32 sys clocks pulse shaper CORE_RST Freescale Semiconductor ...
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... SYS_CLK cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some peripherals (for example, the Flash interface unit) set-up time prior to the 56800E core becoming active. Freescale Semiconductor 56F8013/56F8011 Data Sheet, Rev. 12 Clocks 83 ...
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... Refer to the flash 84 for combined reset extension Switch on falling OSC_CLK 96 MSTR_OSC cycles 32 SYS_CLK cycles delay Switch on falling SYS_CLK 56F8013/56F8011 Data Sheet, Rev. 12 Switch on falling SYS_CLK 32 SYS_CLK cycles delay Freescale Semiconductor ...
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... The command Unlock_Flash_on_Connect1 in the .cfg file accomplishes the same task as using the Debug menu. This lockout recovery mechanism also includes the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared). Freescale Semiconductor sequence via JTAG, 56F8013/56F8011 Data Sheet, Rev ...
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... Peripheral User Manual. 8.2 Configuration There are four GPIO ports defined on the 56F8013/56F8011. The width of each port, the associated peripheral and reset functions are shown in in Table 8-2. 86 Table 8-1. The specific mapping of GPIO port pins is shown 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... PWM5 / FAULT2 / T3 GPIOA6 FAULT0 GPIOA7 RESET GPIOB0 SCLK / SCL GPIOB1 SS / SDA GPIOB2 MISO / T2 Freescale Semiconductor Table 8-1 GPIO Ports Configuration Peripheral Function PWM, Reset SPI, SCI, Timer ADC (GPIOC3 and GPIOC7 are not bonded out on the 56F8013/56F8011) JTAG LQFP Package Pin 29 ...
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... TXD and SCL Defaults to B7 Defaults to ANA0 Defaults to ANA1 Defaults to ANA2 Not bonded out in 56F8013/56F8011 Defaults to ANA3 Defaults to ANB0 Defaults to ANB1 Defaults to ANB2 Not bonded out in 56F8013/56F8011 Defaults to ANB3 Defaults to TDI Defaults to TDO Defaults to TCK Defaults to TMS 8-1 through 8-4 Freescale Semiconductor summarize ...
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... Add. Register Acronym 15 Offset GPIOA_PUPEN GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT GPIOA_IEN GPIOA_IEPOL GPIOA_IPEND GPIOA_IEDGE GPIOA_PPOUTM GPIOA_RDATA GPIOA_DRIVE Figure 8-1 GPIOA Register Map Summary Freescale Semiconductor Read as 0 Reserved Reset 56F8013/56F8011 Data Sheet, Rev. 12 Reset Values IEN IEPOL IPR IES OEN RAW DATA ...
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... Add. Register Acronym 15 Offset GPIOB_PUPEN GPIOB_DATA GPIOB_DDIR GPIOB_PEREN GPIOB_IASSRT GPIOB_IEN GPIOB_IEPOL GPIOB_IPEND GPIOB_IEDGE GPIOB_PPOUTM GPIOB_RDATA GPIOB_DRIVE Figure 8-2 GPIOB Register Map Summary Read as 0 Reserved Reset 56F8013/56F8011 Data Sheet, Rev IEN IEPOL IPR IES OEN RAW DATA DRIVE Freescale Semiconductor ...
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... Add. Register Acronym 15 Offset GPIOC_PUPEN GPIOC_DATA GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT GPIOC_IEN GPIOC_IEPOL GPIOC_IPEND GPIOC_IEDGE GPIOC_PPOUTM GPIOC_RDATA GPIOC_DRIVE Figure 8-3 GPIOC Register Map Summary Freescale Semiconductor Read as 0 Reserved Reset 56F8013/56F8011 Data Sheet, Rev. 12 Reset Values IEN IEPOL IPR IES OEN RAW DATA ...
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... Add. Register Acronym 15 Offset GPIOD_PUPEN GPIOD_DATA GPIOD_DDIR GPIOD_PEREN GPIOD_IASSRT GPIOD_IEN GPIOD_IEPOL GPIOD_IPEND GPIOD_IEDGE GPIOD_PPOUTM GPIOD_RDATA GPIOD_DRIVE Read as 0 Reserved Reset 56F8013/56F8011 Data Sheet, Rev IEN IEPOL IPR IES OEN RAW DATA DRIVE Freescale Semiconductor ...
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... 0V SSA DD DDA Note: The 56F8011 device is specified to meet Industrial requirements only. Freescale Semiconductor are stress ratings only, and functional operation at the maximum = 3.0–3.6V, CL < 50pF 32MHz OP 56F8013/56F8011 Data Sheet, Rev. 12 56F8013/56F8011 Information in the package ...
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... Data Sheet, Rev. 12 higher than Min Max Unit -0.3 4.0 - 0.3 4.0 - 0.3 4.0 - 0.3 0.3 - 0.3 0.3 - 0.3 6.0 - 0.3 4 -20 mA -0.3 4.0 -0.3 6.0 -40 125 °C -40 105 °C -40 150 °C -40 125 °C -55 150 °C -55 150 °C Freescale Semiconductor ...
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... Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 7. See Section 12.1 for more details on thermal design considerations. Freescale Semiconductor Min Typ 2000 — ...
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... V DDA -0.1 0 0.1 -0.1 0 0.1 — — 5.5 -0.3 — 0.8 — — -4 — — -8 — — 4 — — 8 -40 — 125 -40 — 105 10,000 — — 15 — — 20 — — Freescale Semiconductor Unit MHz °C °C Cycles Years Years ...
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... Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC Analog Inputs 2.0 0.0 - 2.0 - 4.0 - 6.0 - 8.0 - 10.0 0.0 0.5 1.0 Figure 10-1 I Freescale Semiconductor At Recommended Operating Conditions Symbol Notes Min V Pin Group 1 2 Pin Groups 1, 2 — Pin Groups 1, 2 — ...
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... No DC Loads 98 Conditions 56F8013/56F8011 Data Sheet, Rev. 12 Typical @ 3.3V, 25°C Maximum@ 3.6V, 25° DDA DD DD 42mA 13.5mA — 17mA 0μA — 0μA 5mA — 430μA 0μA 550μA 300μA 0μA 400μA Freescale Semiconductor I DDA — — — 1μA 1μA ...
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... Short Circuit Tolerance (output shorted to ground) 10.3 AC Electrical Characteristics Tests are conducted using the input levels specified in propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Freescale Semiconductor Symbol 1 V EI3 E12 ...
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... Figure 10-3 Signal States Table 10-9 Flash Timing Parameters Symbol Min T 20 prog T 20 erase T 100 me 56F8013/56F8011 Data Sheet, Rev. 12 High 90% 50% 10% Rise Time and Data3 Valid Data3 Data Active Typ Max Unit μs — 40 — — ms — — ms Freescale Semiconductor ...
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... PLL 1 PLL output frequency (24 x reference frequency) 2 PLL lock time Cycle-to-cycle jitter 1. The core system clock will operate at 1/6 of the PLL output frequency. 2. This is the time required after the PLL is enabled to ensure reliable operation. Freescale Semiconductor Symbol Min 2 f osc t 6.25 PW ...
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... SCI requirements See Figure 10-5. 102 Symbol Minimum f — — roscs t — jitterrosc 56F8013/56F8011 Data Sheet, Rev. 12 Typical Maximum Unit — 8.05 MHz 200 kHz 1 3 µs 400 ps . +1.0 to –1.5 +3.0 to –3 +2.0 to –2.0 % +1.0 to -1.5 +3.0 to –4.5 % Freescale Semiconductor ...
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... Delay from Interrupt Assertion to Fetch of first instruction (exiting Stop the formulas clock cycle and T (used during Reset and Stop modes 125ns. 2. Parameters listed are guaranteed by design. 3. During Power-On Reset possible to use the 56F8013/56F8011 internal reset stretching circuitry to extend this period to 2^21T. Freescale Semiconductor Degrees C (Junction) Symbol ...
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... GPIO pin (Input) Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive) 104 T IW 56F8013/56F8011 Data Sheet, Rev. 12 Freescale Semiconductor ...
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... Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave Freescale Semiconductor 1 Table 10-14 SPI Timing Symbol Min t C 125 62.5 t ELD — ELG — ...
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... SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-7 SPI Master Timing (CPHA = 0) 106 SS is held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8013/56F8011 Data Sheet, Rev LSB in (ref Master LSB out t R Freescale Semiconductor ...
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... DV MOSI (Output) Figure 10-8 SPI Master Timing (CPHA = 1) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-9 SPI Slave Timing (CPHA = 0) Freescale Semiconductor SS is held High on master MSB in Bits 14– Master MSB out Bits 14– 1 ...
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... Slave MSB out Bits 14– MSB in Bits 14–1 Table 10-15 Timer Timing Symbol Min INHL P 125 OUT P 50 OUTHL 56F8013/56F8011 Data Sheet, Rev ELG Slave LSB out LSB Max Unit See Figure — ns 10-11 — ns 10-11 — ns 10-11 — ns 10-11 Freescale Semiconductor ...
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... Timer Inputs Timer Outputs Freescale Semiconductor P INHL OUTHL OUT Figure 10-11 Timer Timing 56F8013/56F8011 Data Sheet, Rev. 12 Quad Timer Timing P INHL P OUTHL 109 ...
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... TOL_SYNCH T 13 BREAK 11 RXD PW Figure 10-12 RXD Pulse Width TXD PW Figure 10-13 TXD Pulse Width 56F8013/56F8011 Data Sheet, Rev Max Unit See Figure (f /16) Mbps — MAX 1.04/BR ns 10-12 1.04/BR ns 10- Master node bit periods Slave node bit periods Freescale Semiconductor ...
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... If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line 1000 + 250 = 1250ns (according to the Standard mode I rmax SU; DAT released total capacitance of the one bus line in pF. b Freescale Semiconductor 2 Table 10- Timing Standard Mode Minimum Maximum f 0 100 SCL 4 ...
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... SU; STA BR t HIGH Table 10-18 JTAG Timing Symbol Min Max f DC SYS_CLK — — )/2 56F8013/56F8011 Data Sheet, Rev HD; STA SP t SU; STO P 2 Unit See Figure MHz 10-15 — ns 10-15 — ns 10-16 — ns 10- 10- 10- Freescale Semiconductor t BUF S C Bus ...
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... TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) Figure 10-16 Test Access Port Timing Diagram Freescale Semiconductor t DS Input Data Valid t DV Output Data Valid t TS 56F8013/56F8011 Data Sheet, Rev. 12 JTAG Timing t DH 113 ...
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... AIC +/- 3 +/- 5 +/- .6 +/- 1 GUARANTEED +/- 4 +/- 9 +/- 6 +/- 12 1.01 to .99 — V REFH — V DDA 0 +/- 2 0 — — 3 Figure 10-17 — Figure 10-17 — 10.0 Freescale Semiconductor Unit Bits MHz V 3 cycles 3 cycles 3 cycles 3 cycles 5 LSB 5 LSB mV mV — μA μ Ohms Bits ...
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... One aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, V and the ADC clock frequency. REF Freescale Semiconductor 10-1. )/2, while the other charges to the analog input voltage. When the REFL 56F8013/56F8011 Data Sheet, Rev. 12 ...
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... PLL, and voltage references. These sources operate independently of processor state or operating 116 channel mux 125 Ohm equiv resistance ESD Resistor 100 Ohms REFHx REFLx 1 × ( ADC Clock Rate ) 1 56F8013/56F8011 Data Sheet, Rev Singled Ended Mode Differential Mode Singled Ended Mode Differential Mode + + 100 ohm 125 ohm − × Freescale Semiconductor ...
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... For instance, if there is a total of eight PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. Freescale Semiconductor 2 *F CMOS power dissipation corresponding to the Intercept 1 ...
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... Figure 11-1 Top View, 56F8013/56F8011 32-Pin LQFP Package 118 Figure 11-1 shows the package outline for the 32-pin ORIENTATION MARK PIN 25 PIN 1 PIN 17 PIN 9 56F8013/56F8011 Data Sheet, Rev. 12 Table 11-1 lists the pin-out GPIOA3/PWM3 GPIOA2/PWM2 GPIOA4/PWM4/FAULT1/T2 GPIOB0/SCLK/SCL GPIOA5/PWM5/FAULT2/T3 GPIOB4/T0/CLKO GPIOA6/FAULT0 GPIOB2/MISO/T2 Freescale Semiconductor ...
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... GPIOB7 11 TXD,SCL 4 GPIOB5 12 T1,FAULT3 5 ANB0 13 GPIOC4 6 ANB1 14 GPIOC5 7 ANB2 15 V ,GPIOC6 REFL DDA 1.Alternate signals are in iltalic Freescale Semiconductor 56F8013/56F8011 Package and Pin-Out Information Pin Signal Name Signal Name No SSA ANA2 18 V ,GPIOC2 REFH ANA1 19 GPIOC1 ANA0 20 GPIOC0 PWM5,FAULT2, TCK 22 GPIOD2 ...
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... M 12 REF 12 REF N 0.090 0.160 0.004 0.006 P 0.400 BSC 0.016 BSC 0.150 0.250 0.006 0.010 S 9.000 BSC 0.354 BSC S1 4.500 BSC 0.177 BSC V 9.000 BSC 0.354 BSC V1 4.500 BSC 0.177 BSC W 0.200 REF 0.008 REF X 1.000 REF 0.039 REF Freescale Semiconductor ...
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... where Thermocouple temperature on top of package ( T Ψ = Thermal characterization parameter ( Power dissipation in package (W) D Freescale Semiconductor , can be obtained from the equation C/W) . For instance, the user can change the size of the heat θCA ) can be used to determine the junction temperature with C/W) 56F8013/56F8011 Data Sheet, Rev. 12 ...
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... Ensure that capacitor leads and associated printed circuit traces that connect to the chip V pins are as short as possible 122 CAUTION of any voltages (GND) pin SS /V Ceramic and tantalum capacitors tend to provide better DDA SSA. 56F8013/56F8011 Data Sheet, Rev. 12 higher than pin on the 56F8013/56F8011 and DD and V (GND Freescale Semiconductor ...
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... Because the Flash memory is programmed through the JTAG/EOnCE port, SPI, SCI or I should provide an interface to this port if in-circuit Flash programming is desired. Freescale Semiconductor with approximately 100μF, plus the number of 0.1μF ceramic capacitors , V REF ...
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... Data Sheet, Rev. 12 Ambient Temperature Order Number (MHz) Range 32 –40° 125°C MC56F8013MFAE* 32 –40° 125°C S568013MFA00E* 32 –40° 105°C MC56F8013VFAE* 32 –40° 105°C MC56F8011VFAE* Processor Expert Legacy Acronym Acronym ADC_ADCR1 ADC_ADCR1 ADC_ADCR2 ADC_ADCR2 ADC_ADZCC ADC_ADZCC ...
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...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...